VHDL lenguaje para síntesis y modelado de circuitos
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Book |
| Language: | Castellano |
| Published: |
Madrid :
Ra-Ma
1999.
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| Subjects: | |
| See on Universidad de Deusto: | https://oceano.biblioteca.deusto.es/primo-explore/search?query=any,contains,991005727009703351&tab=default_tab&search_scope=deusto_alma&vid=deusto |
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| Item Description: | Indice |
|---|---|
| Physical Description: | XI, 238 p. ; 24 cm. + 1 CD-ROM |
| Bibliography: | p, [231]-232 |
| ISBN: | 9788478973514 |
