| Sumario: | In recent years, the multiprocessor architecture field has witnessed the emergence of new trends in the areas of embedded systems, deep learning accelerators, neuromorphic computing, or integration, as well as of disruptive technologies such as quantum computing. Some have even described the near future as a new golden era for computer architecture as all these novelties are factored in new designs. The interconnect, being at the core of any parallel architecture, is of course impacted by these changes. The packet-switched Network-on-Chip (NoC) paradigm is, perhaps, pushed more than ever by the increasing communication demands of modern parallel architectures in terms of scalability, workload heterogeneity, or security. In response to this, the NoC research community continues to improve existing NoC architectures while delving into the role of emerging technologies such as optics, wireless, or 3D interconnects. In an attempt to capture these trends, the NoCArc workshop keeps evolving and refining its scope to include hot topics such as multi-die networks, NoCs for deep learning accelerators, or in-memory computing.
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