Vertical 3D memory technologies
The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then...
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Chichester, England :
Wiley
2014.
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| Edición: | 1st edition |
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| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009629658106719 |
