Vertical 3D memory technologies
The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then...
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Chichester, England :
Wiley
2014.
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| Edición: | 1st edition |
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009629658106719 |
| Sumario: | The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and doubl |
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| Notas: | Description based upon print version of record. |
| Descripción Física: | 1 online resource (371 p.) |
| Bibliografía: | Includes bibliographical references and index. |
| ISBN: | 9781118760468 9781118760475 9781118760451 |
