Introduction to digital systems modeling, synthesis, and simulation using VHDL
A unique guide to using both modeling and simulation in digital systems design Digital systems design requires rigorous modeling and simulation analysis that eliminates design risks and potential harm to users. Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL introduc...
| Autor principal: | |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Hoboken, N.J. :
Wiley
c2011.
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| Edición: | 1st edition |
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627799306719 |
Tabla de Contenidos:
- Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL; CONTENTS; PREFACE; 1 Digital System Modeling and Simulation; 1.1 OBJECTIVES; 1.2 MODELING, SYNTHESIS, AND SIMULATION DESIGN; 1.3 HISTORY OF DIGITAL SYSTEMS; 1.4 STANDARD LOGIC DEVICES; 1.5 CUSTOM-DESIGNED LOGIC DEVICES; 1.6 PROGRAMMABLE LOGIC DEVICES; 1.7 SIMPLE PROGRAMMABLE LOGIC DEVICES; 1.8 COMPLEX PROGRAMMABLE LOGIC DEVICES; 1.9 FIELD-PROGRAMMABLE GATE ARRAYS; 1.10 FUTURE OF DIGITAL SYSTEMS; PROBLEMS; 2 Number Systems; 2.1 OBJECTIVES; 2.2 BASES AND NUMBER SYSTEMS; 2.3 NUMBER CONVERSIONS; 2.4 DATA ORGANIZATION
- 2.5 SIGNED AND UNSIGNED NUMBERS2.6 BINARY ARITHMETIC; 2.7 ADDITION OF SIGNED NUMBERS; 2.8 BINARY-CODED DECIMAL REPRESENTATION; 2.9 BCD ADDITION; PROBLEMS; 3 Boolean Algebra and Logic; 3.1 OBJECTIVES; 3.2 BOOLEAN THEORY; 3.3 LOGIC VARIABLES AND LOGIC FUNCTIONS; 3.4 BOOLEAN AXIOMS AND THEOREMS; 3.5 BASIC LOGIC GATES AND TRUTH TABLES; 3.6 LOGIC REPRESENTATIONS AND CIRCUIT DESIGN; 3.7 TRUTH TABLE; 3.8 TIMING DIAGRAM; 3.9 LOGIC DESIGN CONCEPTS; 3.10 SUM-OF-PRODUCTS DESIGN; 3.11 PRODUCT-OF-SUMS DESIGN; 3.12 DESIGN EXAMPLES; 3.13 NAND AND NOR EQUIVALENT CIRCUIT DESIGN
- 3.14 STANDARD LOGIC INTEGRATED CIRCUITSPROBLEMS; 4 VHDL Design Concepts; 4.1 OBJECTIVES; 4.2 CAD TOOL-BASED LOGIC DESIGN; 4.3 HARDWARE DESCRIPTION LANGUAGES; 4.4 VHDL LANGUAGE; 4.5 VHDL PROGRAMMING STRUCTURE; 4.6 ASSIGNMENT STATEMENTS; 4.7 VHDL DATA TYPES; 4.8 VHDL OPERATORS; 4.9 VHDL SIGNAL AND GENERATE STATEMENTS; 4.10 SEQUENTIAL STATEMENTS; 4.11 LOOPS AND DECISION-MAKING STATEMENTS; 4.12 SUBCIRCUIT DESIGN; 4.13 PACKAGES AND COMPONENTS; PROBLEMS; 5 Integrated Logic; 5.1 OBJECTIVES; 5.2 LOGIC SIGNALS; 5.3 LOGIC SWITCHES; 5.4 NMOS AND PMOS LOGIC GATES; 5.5 CMOS LOGIC GATES
- 5.6 CMOS LOGIC NETWORKS5.7 PRACTICAL ASPECTS OF LOGIC GATES; 5.8 TRANSMISSION GATES; PROBLEMS; 6 Logic Function Optimization; 6.1 OBJECTIVES; 6.2 LOGIC FUNCTION OPTIMIZATION PROCESS; 6.3 KARNAUGH MAPS; 6.4 TWO-VARIABLE KARNAUGH MAP; 6.5 THREE-VARIABLE KARNAUGH MAP; 6.6 FOUR-VARIABLE KARNAUGH MAP; 6.7 FIVE-VARIABLE KARNAUGH MAP; 6.8 XOR AND NXOR KARNAUGH MAPS; 6.9 INCOMPLETE LOGIC FUNCTIONS; 6.10 QUINE-McCLUSKEY MINIMIZATION; PROBLEMS; 7 Combinational Logic; 7.1 OBJECTIVES; 7.2 COMBINATIONAL LOGIC CIRCUITS; 7.3 MULTIPLEXERS; 7.4 LOGIC DESIGN WITH MULTIPLEXERS; 7.5 DEMULTIPLEXERS; 7.6 DECODERS
- 7.7 ENCODERS7.8 CODE CONVERTERS; 7.9 ARITHMETIC CIRCUITS; PROBLEMS; 8 Sequential Logic; 8.1 OBJECTIVES; 8.2 SEQUENTIAL LOGIC CIRCUITS; 8.3 LATCHES; 8.4 FLIP-FLOPS; 8.5 REGISTERS; 8.6 COUNTERS; PROBLEMS; 9 Synchronous Sequential Logic; 9.1 OBJECTIVES; 9.2 SYNCHRONOUS SEQUENTIAL CIRCUITS; 9.3 FINITE-STATE MACHINE DESIGN CONCEPTS; 9.4 FINITE-STATE MACHINE SYNTHESIS; 9.5 STATE ASSIGNMENT; 9.6 ONE-HOT ENCODING METHOD; 9.7 FINITE-STATE MACHINE ANALYSIS; 9.8 SEQUENTIAL SERIAL ADDER; 9.9 SEQUENTIAL CIRCUIT COUNTERS; 9.10 STATE OPTIMIZATION; 9.11 ASYNCHRONOUS SEQUENTIAL CIRCUITS; PROBLEMS; INDEX
