ASIC and FPGA verification a guide to component modeling
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
| Main Author: | |
|---|---|
| Format: | eBook |
| Language: | Inglés |
| Published: |
San Francisco, CA : Oxford :
Morgan Kaufmann ; Elsevier
c2005.
|
| Series: | Systems on Silicon
|
| Subjects: | |
| See on Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627307306719 |
