ASIC and FPGA verification a guide to component modeling
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
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San Francisco, CA : Oxford :
Morgan Kaufmann ; Elsevier
c2005.
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| Colección: | Systems on Silicon
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| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627307306719 |
