ASIC and FPGA verification a guide to component modeling
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
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| Format: | eBook |
| Language: | Inglés |
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San Francisco, CA : Oxford :
Morgan Kaufmann ; Elsevier
c2005.
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| Series: | Systems on Silicon
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| Subjects: | |
| See on Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627307306719 |
| Summary: | Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.<br |
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| Item Description: | Description based upon print version of record. |
| Physical Description: | 1 online resource (337 p.) |
| ISBN: | 9781281008282 9786611008284 9780080475929 |
