Verilog Coding for Logic Synthesis
Provides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micr...
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
[Place of publication not identified]
Wiley Interscience Imprint
2003
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| Edición: | 1st edition |
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627036806719 |
| Sumario: | Provides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. Book is suitable for use as a textbook in EE departments that have VLSI courses |
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| Notas: | Bibliographic Level Mode of Issuance: Monograph |
| Descripción Física: | 1 online resource (1 v.) : ill |
| Bibliografía: | Includes bibliographical references and index. |
| ISBN: | 9781280556524 9786610556526 9780471457558 9780470356920 9780471457565 |
