Tabla de Contenidos: “…Flat-Panel DisplaysLiquid Crystal Display Panels; Thin Film Transistor LCDs; Plasma Screens; Organic Light-Emitting Diodes Displays; Shelf-Oriented Digital Signage Systems; Projectors; LCD Projectors; Digital Light-Processing Projectors; Short-Range Projection Systems; Outdoor Display Systems; LED Outdoor Display Systems; Daylight-Use LCD Display Systems; Transreflective and Reflective LCDs; Screen Orientation and Aspect Ratios; Display Device Resolution; Computer Display Devices; High-Definition Television; Other Display Aspects; Display System Interfaces; Other Kinds of Display Devices…”

Tabla de Contenidos: “…Cover -- Half Title -- Title Page -- Copyright Page -- Table of Contents -- Preface -- Acknowledgments -- Author -- Chapter 1: CMOS Analog and Mixed-Signal Circuit Design: An Overview -- 1.1 Introduction -- 1.2 Notation, Symbol, and Terminology -- 1.3 Technology, Circuit Topology, and Methodology -- 1.4 Analog and Mixed-Signal Integrated Design Concepts -- 1.5 Summary -- Chapter 2: Devices: An Overview -- 2.1 Introduction -- 2.2 The PN Junction -- 2.2.1 Fermi Level -- 2.2.2 Depletion Layer Capacitance -- 2.2.3 Storage Capacitance -- 2.3 Photo Devices -- 2.4 FETs -- 2.4.1 Long Channel Approximation -- 2.4.1.1 MOS Structure -- 2.4.1.2 MOS with External Bias -- 2.4.1.3 MOS Operation -- 2.4.1.4 Current-Voltage Characteristics -- 2.4.2 MOSFET Scaling -- 2.4.2.1 Full Scaling -- 2.4.2.2 Constant-Voltage Scaling -- 2.4.3 Weak Inversion -- 2.4.4 Short-Channel -- 2.4.4.1 Carrier Drift Velocity Models -- 2.4.4.2 VDSAT -- 2.4.4.3 Current-Voltage Equation for Short Channel Transistor -- 2.4.5 MOSFET Capacitor -- 2.4.5.1 Oxide-Related Capacitance -- 2.4.5.2 Junction Capacitance -- 2.4.6 MOSFET Transition Frequency -- 2.4.7 Noise -- 2.4.7.1 Thermal Noise -- 2.4.7.2 Flicker Noise -- 2.5 Process Fitting Ratio -- 2.5.1 150-90 nm Design Transfer -- 2.6 MOSFET Parameter Exercise -- 2.7 SPICE Example -- 2.8 Summary -- References -- Chapter 3: Amplifiers -- 3.1 Introduction -- 3.1.1 CMOS Amplifier -- 3.2 Input Voltage Range -- 3.2.1 Theory -- 3.2.2 Example -- 3.3 Signal Path of CMOS Operational Amplifier -- 3.3.1 Overall Signal Path -- 3.3.2 Load -- 3.3.3 Cascode Current Source -- 3.3.4 Example -- 3.4 CMOS Amplifier Parameters -- 3.4.1 Input Offset -- 3.4.2 Common Mode Input Voltage Range -- 3.4.3 Current Consumption -- 3.4.4 Common Mode Rejection Ratio (CMRR) -- 3.4.5 Power Supply Rejection Ratio -- 3.4.6 Slew Rate and Settling Time -- 3.4.7 DC Gain, fs, and fT…”

Tabla de Contenidos: “…Simplificación de funciones lógicas por el método de KarnaughEl transistor como interruptor; Familias de circuitos integrados digitales; Circuitos de pulsos; Circuito integrado 555; 10 Interruptores y relés; ¿Qué es un interruptor?…”

Tabla de Contenidos: “…Analysis of failures of the set converter-machine: converters with MOSFET transistors; 3.2. Analysis of the main causes of failure; 3.2.1. …”

Tabla de Contenidos: “…Front Cover; Op Amps for Everyone; Copyright Page; Contents; List of Figures; List of Tables; List of Abbreviations; 1 The Op Amp's Place in the World; 1.1 An Unbounded Gain Problem; 1.2 The Solution; 1.3 The Birth of the Op Amp as a Component; 1.3.1 The Vacuum Tube Era; 1.3.2 The Transistor Era; 1.3.3 The Integrated Circuit Era; Reference; 2 Review of Op Amp Basics; 2.1 Introduction; 2.2 Basic Concepts; 2.2.1 Ohm's Law; 2.2.2 The Voltage Divider Rule; 2.2.3 Superposition; 2.3 Basic Op Amp Circuits; 2.3.1 The Non-Inverting Op Amp; 2.3.2 The Inverting Op Amp; 2.3.3 The Adder…”

Tabla de Contenidos: “…Técnicas; 9 Osciladores sinusoidales con transistores (...); 9.1 Introducción y objetivos; 9.2 Principios. …”

Tabla de Contenidos: “….) -- ARQUITECTURA DE VON NEUMANN -- LOS TRANSISTORES. ORDENADORES DE SEGUNDA GENERACIÓN -- LOS CIRCUITOS INTEGRADOS. …”

Tabla de Contenidos: “…REPARANDO FUENTES CONMUTADAS; PÁGINA LEGAL; CONTENIDO; CAPÍTULO 1 Fuentes Primarias; Bloques Básicos; Puente Rectificador y Filtrado; Evaluación de los Capacitores Electrolíticos; Contactos Transitorios; Circuito Desmagnetizador; CAPÍTULO 2 SISTEMAS DE REGULACIÓN LINEAL; Introducción; Circuitos Básicos y Comerciales; Precauciones Durante la Reparación; CAPÍTULO 3 FUENTES CONMUTADAS I; Introducción; Circuitos de Control, Regulación y Protección; Circuito de Control; Arranque y Alimentación; Regulación; Protección; Excitador de Conmutación; Circuito Primario y Transistor de Potencia…”

Tabla de Contenidos: “…-- 1.5 SUMMARY -- 1.6 PROBLEMS -- Chapter 2 Semiconductor Devices from a Circuit-Theoretic Standpoint -- 2.1 LINEAR CIRCUIT ELEMENTS -- 2.1.1 Linear Resistors -- 2.1.2 Linear Capacitors -- 2.1.3 Linear Inductors -- 2.2 NONLINEAR CIRCUIT ELEMENTS -- 2.2.1 Nonlinear Resistors -- 2.2.2 Nonlinear Capacitors and Inductors -- 2.3 TIME-INVARIANT AND TIME-VARYING CIRCUIT ELEMENTS -- 2.4 MULTITERMINAL ELEMENTS AND CONTROLLED SOURCES -- 2.5 TRANSISTORS -- 2.6 CIRCUIT-THEORETIC POSITIONING OF SEMICONDUCTOR DEVICES -- 2.7 SUMMARY -- 2.8 PROBLEMS -- Chapter 3 Waves in Periodic Structures -- 3.1 ANALOGIES IN PHYSICS -- 3.1.1 Commonality of Mathematical Structures -- 3.1.2 Overview of the Chapter -- 3.2 PROPERTIES OF PERIODIC NETWORKS -- 3.2.1 Infinitely Long Ladder Networks -- 3.2.2 Infinitely Long LC Ladders -- 3.2.3 Lossless Transmission Lines -- 3.2.4 Periodic Networks with a Finite Number of Repetitions -- 3.2.5 Kronig-Penney Model -- 3.3 DISPERSION RELATION AND PHASE AND GROUP VELOCITIES -- 3.3.1 Dispersion Relation -- 3.3.2 Phase Velocity and Group Velocity -- 3.3.3 Calculation of the Dispersion Relation -- 3.4 DISPERSION RELATION AND PROPERTIES OF SEMICONDUCTORS -- 3.5 BRAGG REFLECTION -- 3.6 SUMMARY -- 3.7 PROBLEMS -- Chapter 4 Physics of Semiconductors in Equilibrium…”

Tabla de Contenidos: “…Front Cover -- Three-Dimensional Integrated Circuit Design -- Copyright Page -- Dedication -- Contents -- List of Figures -- About the Authors -- Preface to the Second Edition -- Preface to the First Edition -- Acknowledgments -- Organization of the Book -- 1 Introduction -- 1.1 Interconnect Issues in Integrated Systems -- 1.2 Three-Dimensional or Vertical Integration -- 1.2.1 Opportunities for Three-Dimensional Integration -- 1.2.2 Challenges of Three-Dimensional Integration -- 1.2.2.1 Technological/manufacturing limitations -- 1.2.2.2 Testing -- 1.2.2.3 Global interconnect design -- 1.2.2.4 Thermal issues -- 1.2.2.5 CAD algorithms and tools -- 1.3 Book Organization -- 2 Manufacturing of Three-Dimensional Packaged Systems -- 2.1 Stacking Methods for Transistors, Circuits, and Dies -- 2.1.1 System-in-Package -- 2.1.2 Transistor and Circuit Level Stacking -- 2.2 System-on-Package -- 2.3 Technologies for System-in-Package -- 2.3.1 Wire Bonded System-in-Package -- 2.3.2 Peripheral Vertical Interconnects -- 2.3.3 Area Array Vertical Interconnects -- 2.3.4 Metalizing the Walls of an SiP -- 2.4 Technologies for 2.5-D Integration -- 2.4.1 Interposer Materials -- 2.4.2 Metallization Processes -- 2.4.3 Vertical Interconnects -- 2.5 Summary -- 3 Manufacturing Technologies for Three-Dimensional Integrated Circuits -- 3.1 Monolithic Three-Dimensional ICs -- 3.1.1 Laser Crystallization -- 3.1.2 Seed Crystallization -- 3.1.3 Double-Gate Metal Oxide Semiconductor Field Effect Transistors for Stacked Three-Dimensional ICs -- 3.1.4 Molecular Bonding -- 3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via -- 3.2.1 Wafer Level Integration -- 3.2.2 Die-to-Die Integration -- 3.2.3 Bonding of Three-Dimensional ICs -- 3.3 Contactless Three-Dimensional ICs -- 3.3.1 Capacitively Coupled Three-Dimensional ICs…”

“….; the capacitance and inductance in a.c. circuits; and the capacitance and inductance in a series. Diodes, triode, transistor equivalent…”

Tabla de Contenidos: “…Preface xi -- Acknowledgments xiii -- About the Author xv -- About the Reviewers xvii -- Note to Instructors xxi -- 1 HOW TO DESIGN RESISTIVE CIRCUITS 1 -- 1.1 Design of a Resistive Thevenin Source 2 -- 1.2 Design of a Coupling Circuit 4 -- 1.3 Design of a Pi Attenuator 8 -- Problems 14 -- References 17 -- 2 HOW TO PREVENT A POWER TRANSISTOR FROM OVERHEATING 19 -- 2.1 Electrical Model for Heat Transfer 20 -- 2.2 Using Manufacturer's Data for Thermal Analysis 23 -- 2.3 Forced-Air Cooling 26 -- 2.4 Dynamic Response of a Thermal System 27 -- Problems 30 -- Reference 32 -- 3 HOW TO ANALYZE A CIRCUIT 33 -- 3.1 Frequency Response of a Transfer Function 34 -- 3.2 Frequency Response and Impedance of Simple Circuits 38 -- 3.3 Frequency Response for Ladder Networks 51 -- 3.4 Generalized Technique for Determining Frequency Response 54 -- Problems 58 -- References 60 -- 4 HOW TO USE STATISTICS TO ENSURE A MANUFACTURABLE DESIGN 61 -- 4.1 Independent Component Failures 62 -- 4.2 Using the Gaussian Distribution 63 -- 4.3 Setting a Manufacturing Test Limit 68 -- 4.4 Procuring a Custom Component 71 -- Problems 76 -- References 77 -- 5 HOW TO DESIGN A FEEDBACK CONTROL SYSTEM 79 -- 5.1 Intuitive Description of a Control System 80 -- 5.2 Review of Control System Operation 81 -- 5.3 Performance of Control Systems 84 -- 5.4 First-Order Control System Design 84 -- 5.5 Second-Order Control System Design 88 -- 5.6 Circuit Realization of a Second-Order Control System 94 -- 5.7 First-Order Discrete Control System 95 -- Problems 101 -- References 102 -- 6 HOW TO WORK WITH OP-AMP CIRCUITS 103 -- 6.1 The Ideal Op-Amp 104 -- 6.2 Practical Op-Amps 108 -- 6.2.1 Effect of Input Offset Voltage 108 -- 6.2.2 Noise Contribution from Op-Amp Circuits 110 -- 6.2.3 Dynamic Characteristics of Op-Amp Circuits 113 -- 6.2.4 Effect of Capacitive Loading 116 -- 6.2.5 A Nagging Issue 118 -- Problems 119 -- References 121 -- 7 HOW TO DESIGN ANALOG FILTERS 123 -- 7.1 Passive Versus Active Filters 124 -- 7.2 The Lowpass RC Filter 125.…”

Tabla de Contenidos: “…LOCOS-bound Lateral N-Well to N-Well Bipolar ESD Element 738 16.13 LOCOS-bound Lateral N+ to N-well Bipolar ESD Element 738 16.14 LOCOS-bound Lateral pnp Bipolar ESD Element 739 16.15 LOCOS-bound Thick Oxide MOSFET ESD Element 739 16.16 Shallow Trench Isolation 739 16.17 STI-bound ESD Structures 741 16.18 Substrate Modeling - Electrical and Thermal Discretization 746 16.19 Heavily Doped Substrates 750 16.20 Retrograde Wells and ESD Scaling 766 16.21 Triple Well and Isolated MOSFET CMOS 775 16.22 Summary and Closing Comments 779 References 779 17 ESD in Silicon on Insulator 783 17.1 Silicon on Insulator (SOI) Technologies 783 17.2 Elimination of CMOS Latchup 784 17.3 Lack of Vertical Bipolar Transistors 785 17.4 Floating Gate Tie Downs 785 17.5 Physical Separation of MOSFETs from the Bulk Substrate 785 17.6 SOI ESD Design Fundamental Concepts 786 17.7 SOI Lateral Diode Structure 791 17.8 Transistors - Bulk versus SOI Technology 791 17.9 SOI Buried Resistors (BR) Elements 796 17.10 Dynamic Threshold MOS (DTMOS) SOI MOSFET 797 17.11 SOI P+ Body Contact Abutting n+ Drain 798 17.12 Transmission Line Pulse (TLP) Testing of SOI Diode Designs 798 17.13 SOI ESD with MOSFET Drain and Body Width Ratio Variation 799 17.14 SOI Dual-Gate MOSFET Structure 799 17.15 SOI ESD Design - Mixed Voltage T-Shape Layout Style 800 17.16 SOI ESD Design: Double Diode Network 802 17.17 Bulk to SOI ESD Design Remapping 803 17.18 SOI ESD Diode Design Parameters 804 17.19 SOI ESD Design in Mixed Voltage Interface Environments 808 17.20 Comparison of Bulk with SOI ESD Results 809 17.21 SOI ESD Design with Aluminum Interconnects 810 17.22 SOI ESD Design with Copper Interconnects 812 17.23 SOI ESD Design with Gate Circuitry 813 17.24 Summary and Closing Comments 815 References 815 18 ESD in Analog Circuits 821 18.1 Analog Design Circuits 821 18.2 Single-ended Receivers 822 18.3 Schmitt Trigger Receivers 822 18.4 Differential Receivers 822 18.5 Comparators 824 18.6 Current Sources 825 18.7 Current Mirrors 825 18.8 Widlar Current Mirror 826 18.9 Wilson Current Mirror 826 18.10 Voltage Regulators 827 18.11 Buck Converters 828 18.12 Boost Converters 828 18.13 Buck-Boost Converters 829 18.14 Cuk Converters 830 18.15 Voltage Reference Circuits 830 18.16 Brokaw Bandgap Voltage Reference 830 18.17 Converters 831 18.18 Analog-to-Digital Converter (ADC) 831 18.19 Digital-to-Analog Converters (DAC) 832 18.20 Oscillators 832 18.21 Phase Lock Loop (PLL) Circuits 832 18.22 Delay Locked Loop (DLL) 833 18.23 Analog and ESD Design Synthesis 833 18.24 Analog Chip Architecture - Separation of Analog Power from Digital Power, AVDD-DVDD 836 18.25 ESD Failure in Phase Lock Loop (PLL) and System Clock 837 18.26 ESD Failure in Current Mirrors 837 18.27 ESD Failure in Schmitt Trigger Receivers 838 18.28 ESD Design Practice - Prevent ESD Failure in Schmitt Trigger 840 18.29 Analog-Digital Architecture: Isolated Digital and Analog Domains 841 18.30 ESD Protection Solution - Connectivity of AVDD-to-VDD 842 18.31 ESD Solution: Connectivity of AVSS-to-DVSS 843 18.32 Digital and Analog Domain with ESD Power Clamps 843 18.33 Digital and Analog Domain with Master-Slave ESD Power Clamps 846 18.34 High Voltage, Digital, and Analog Domain Floorplan 846 18.35 Floor-planning of Digital and Analog 846 18.36 Inter-domain Signal Lines ESD Failures 849 18.37 Digital-to-Analog Signal Line ESD Failures 849 18.38 Digital-to-Analog Core Spatial Isolation 851 18.39 Digital-to-Analog Core Ground Coupling 851 18.40 Digital-to-Analog Core Resistive Ground Coupling 852 18.41 Digital-to-Analog Core Diode Ground Coupling 852 18.42 Domain-to-Domain Signal Line ESD Networks 852 18.43 Domain-to-Domain Third-party Coupling Networks 853 18.44 Domain-to-Domain Cross-domain ESD Power Clamp 854 18.45 Digital-to-Analog Domain Moat 855 18.46 Analog and ESD Circuit Integration 855 18.47 Integrated Body Ties 856 18.48 Self-Protecting vs Non-self Protecting Designs 856 References 856 19 ESD in RF CMOS 865 19.1 CMOS and ESD 865 19.2 RF CMOS 865 19.3 RF CMOS and ESD 865 19.4 RF CMOS ESD Failure Mechanisms 865 19.5 RF CMOS - ESD Device Comparisons 866 19.6 RF ESD Metrics 867 19.7 Grounded Gate n-channel MOSFET versus STI Diode 868 19.8 Silicon-controlled Rectifier 869 19.9 SCR versus GGNMOS 869 19.10 Shallow Trench Isolation and Polysilicon Gated Diodes 869 19.11 RF ESD Design 870 19.12 RF ESD Design Layout - Circular RF ESD Devices 870 19.13 Disadvantage of RF ESD Circular Element 871 19.14 RF ESD Design - ESD Wiring Design 872 19.15 RF ESD Design - Loading Capacitance 872 19.16 Metal Capacitance 873 19.17 Analog Metal (AM) 873 19.18 RF ESD Design Practices 874 19.19 RF Passives - ESD and Schottky Barrier Diodes 874 19.20 Schottky Barrier Diodes and Metallurgy 875 19.21 Silicon Germanium Schottky Barrier Diodes 876 19.22 Schottky Barrier RF ESD Design Practice 877 19.23 RF Passives - ESD and Inductors 877 19.24 Quality Factor, Q 878 19.25 Incremental Model of an Inductor 878 19.26 Inductor Coil Parameters 878 19.27 RF Passives - ESD and Capacitors 882 19.28 Capacitors and RF Applications 882 19.29 Capacitors in ESD Networks 882 19.30 Types of Radio Frequency Capacitors 883 19.31 Metal-Oxide-Semiconductor and Metal-Insulator-Metal Capacitors 883 19.32 Varactors and Hyper-abrupt Junction Varactor Capacitors 884 19.33 Metal-ILD-Metal Capacitors 884 19.34 Vertical Parallel Plate (VPP) Capacitors 884 19.35 Tips: ESD RF Design Practices for Capacitors 885 19.36 Summary and Closing Comments 886 Problems 886 References 888 20 ESD in Silicon Germanium 891 20.1 Heterojunctions Bipolar Transistors 891 20.2 Silicon Germanium 891 20.3 Silicon Germanium HBT Devices 892 20.4 Silicon Germanium Device Structure 893 20.5 Silicon Germanium Film Deposition 894 20.6 Silicon Germanium Emitter-Base Region 895 20.7 Silicon Germanium Physics 895 20.8 Silicon Germanium Bandgap 896 20.9 Silicon Germanium Intrinsic Temperature 896 20.10 Position-dependent Silicon Germanium Profile 896 20.11 Position-dependent Intrinsic Temperature 897 20.12 SiGe Collector Current with Graded Germanium Concentration 897 20.13 Silicon Germanium ESD and Time Constants 898 20.14 Silicon Germanium Base Transit Time 898 20.15 Silicon Germanium Breakdown Voltages 898 20.16 Silicon Germanium ESD Measurements 899 20.17 Silicon Germanium Collector-to-Emitter ESD Stress 899 20.18 Transmission Line Pulse Testing of Silicon Germanium HBT 899 20.19 Transmission Line Pulse (TLP) I-V Characteristic 899 20.20 Wunsch-Bell Characteristic of Silicon Germanium HBT 901 20.21 Comparison of Silicon Germanium HBT and Silicon BJT 901 20.22 Wunsch-Bell Characteristic of SiGe HBT versus Si BJT 902 20.23 Intrinsic Base Resistance in SiGe HBT 904 20.24 SiGe HBT Electro-thermal HBM Simulation of Collector-Emitter Stress 904 20.25 Silicon Germanium Transistor Emitter-Base Design 905 20.26 Epitaxial-Base Hetero-Junction Bipolar Transistor (HBT) Emitter-Base Design 907 20.27 Self-aligned Silicon Germanium HBT Device 907 20.28 Non-Self Aligned Silicon Germanium HBT 908 20.29 Emitter-Base Design RF Frequency Performance Metrics 908 20.30 SiGe HBT Emitter-Base Resistance Model 909 20.31 SiGe HBT Emitter-Base Design and Silicide Placement 909 20.32 Silicide Material and ESD 910 20.33 Titanium Silicide and ESD 911 20.34 Cobalt Salicide 913 20.35 Self-aligned (SA) Emitter Base Design 914 20.36 Non-Self Aligned (NSA) Emitter Base Design 917 20.37 Non-Self Aligned HBT Human Body Model (HBM) Step Stress 918 20.38 Transmission Line Pulse (TLP) Step Stress 918 20.39 RF Testing of SiGe HBT Emitter-Base Configuration 921 20.40 Unity Current Gain Cutoff Frequency - Collector Current Plots 923 20.41 f MAX and f T 924 20.42 Electrothermal Simulation of Emitter-Base Stress 925 20.43 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data 926 20.44 Silicon Germanium HBT Multiple-emitter Study 927 20.45 RF ESD Design Practice 927 20.46 Silicon Germanium ESD Failure Mechanisms 928 20.47 Summary and Closing Comments 928 References 928 21 ESD in Silicon Germanium Carbon 935 21.1 Heterojunctions and Silicon Germanium Carbon Technology 935 21.2 Silicon Germanium Carbon 935 21.3 Silicon Germanium Carbon Collector-Emitter ESD Measurements 937 21.4 Silicon Germanium Transistor Emitter-Base Design 940 21.5 Silicon Germanium Carbon - ESD-Induced S-Parameter Degradation 943 21.6 Silicon Germanium Carbon ESD Failure Mechanisms 945 21.7.…”

Tabla de Contenidos: “…ABUNDAN LOS YACIMIENTOSENERGÍA QUE NO SE AGOTA, SIMPLE Y BARATA; MÚLTIPLES APLICACIONES; LA IRRUPCIÓN DE LAS CALCULADORAS MANUALES: UN CEREBRO ELECTRÓNICO EN CADA BOLSILLO; CADA VEZ MÁS EN CADA VEZ MENOS SITIO; LA ERA DEL TRANSISTOR; SE IMPRIMEN APARATOS ELECTRÓNICOS; LA ELECTRÓNICA OMNIPRESENTE; EL VIDEODISCO; 45.000 ESPIRAS EN CADA CARA; ¿QUÉ GRABAREMOS?…”

Tabla de Contenidos: “…2 >> Cálculo de circuitos eléctricos con agrupación de resistencias3 >> Caída de tensión en un circuito; 4 >> Comparación de circuitos con resistencias en serie y en paralelo; 5 >> Lectura de intensidad, resistencia y voltaje con el polímetro; UNIDAD 3; 1 >> Los imanes; 2 >> Electromagnetismo; 3 >> Componentes magnéticos en circuitos eléctricos; UNIDAD 4; 1 >> Generación de corriente eléctrica; 2 >> Aparatos eléctricos; UNIDAD 5; 1 >> Materiales semiconductores; 2 >> El diodo; 4 >> El transistor; 5 >> Tiristor; 6 >> Efecto Hall; 7 >> Pinza amperimétrica; UNIDAD 6…”

Tabla de Contenidos: “…Introducción a la inteligencia artificial; 1.Neuronas y transistores; 2.Breve historia de la IA; 3. Ámbitos de aplicación de la inteligencia artificial; Capítulo II. …”

Tabla de Contenidos: “…1 >> Agrupación de resistencias en serie, paralelo y mixtas2 >> Cálculo de circuitos eléctricos con agrupación de resistencias; 3 >> Caída de tensión en un circuito; 4 >> Comparación de circuitos con resistencias en serie y en paralelo; 5 >> Lectura de intensidad, resistencia y voltaje con el polímetro; UNIDAD 3; 1 >> Los imanes; 2 >> Electromagnetismo; 3 >> Componentes magnéticos en circuitos eléctricos; UNIDAD 4; 1 >> Generación de corriente eléctrica; 2 >> Aparatos eléctricos; UNIDAD 5; 1 >> Materiales semiconductores e-; 2 >> El diodo; 3 >> Diodos especiales; 4 >> El transistor…”

Tabla de Contenidos: “…2 >> Càlcul de circuits elèctrics amb agrupació de resistències3 >> Caiguda de tensió en un circuit; 4 >> Comparació de circuits amb resistències en sèrie i en paral·lel; 5 >> Lectura d'intensitat, resistència i voltatge amb el polímetre; UNITAT 3; 1 >> Els imants; 2 >> Electromagnetisme; 3 >> Components magnètics en circuits elèctrics; UNITAT 4; 1 >> Generació de corrent elèctric; 2 >> Aparells elèctrics; UNITAT 5; 1 >> Materials semiconductors; 2 >> El díode; 3 >> Díodes especials; 4 >> El transistor; 5 >> El tiristor; 6 >> Efecte Hall; 7 >> Pinça amperimètrica; UNITAT 6…”

Tabla de Contenidos: “…Bruns -- The refuge relay function generator / K.B. Tuttle -- A transistor operational d.c. amplifier / W. Hochwald, F.H. …”

Tabla de Contenidos: “…Chip Perception; 8.1.1 Contrast-dependent speed perception; 8.1.2 Bias on perceived direction of motion; 8.1.3 Perceptual dynamics; 8.2 Computational Architecture; 8.3 Remarks; Appendix; A Variational Calculus; B Simulation Methods; C Transistors and Basic Circuits; D Process Parameters and Chips Specifications; References; Index…”