Tabla de Contenidos: “…Shunt Failure 450 10.20 ESD Clamp Element - Width Scaling 450 10.21 ESD Clamp Element - On-resistance 450 10.22 ESD Clamp Element - Safe Operating Area (SOA) 451 10.23 ESD Power Clamp Issues 451 10.24 ESD Power Clamp Issues - Power-up and Power-down 451 10.25 ESD Power Clamp Issues - False Triggering 452 10.26 ESD Power Clamp Issues - Pre-charging 452 10.27 ESD Power Clamp Issues - Post-charging 452 10.28 ESD Power Clamp Design 453 10.29 ESD Power Clamp Design Synthesis - Forward Bias Triggered ESD Power Clamps 456 10.30 Series Stacked RC-triggered ESD Power Clamps 459 10.31 Triple Well Diode String ESD Power Clamp 463 10.32 Bipolar ESD Power Clamps 464 10.33 ESD Power Clamp Design Synthesis - Bipolar ESD Power Clamps 469 10.34 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance-triggered 480 10.35 Silicon Controlled Rectifier Power Clamps 481 References 486 11 ESD Architecture and Floor Planning 491 11.1 ESD Design Floor Plan 491 11.2 Peripheral I/O Design 492 11.3 Pad Limited Peripheral I/O Design Architecture 493 11.4 Pad Limited Peripheral I/O Design Architecture - Staggered I/O 493 11.5 Core Limited Peripheral I/O Design Architecture 495 11.6 Lumped ESD Power Clamp in Peripheral I/O Design Architecture 496 11.7 Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners 496 11.8 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Power Pads 497 11.9 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Master/Slave ESD Power Clamp System 498 11.10 Array I/O 498 11.11 Array I/O Nibble Architecture 501 11.12 Array I/O Pair Architecture 503 11.13 Array I/O - Fully Distributed 504 11.14 ESD Architecture - Dummy Bus Architecture 507 11.15 ESD Architecture - Dummy VDD Bus 507 11.16 ESD Architecture - Dummy Ground (VSS) Bus 508 11.17 Native Voltage Power Supply Architecture 508 11.18 Single Power Supply Architecture 509 11.19 Mixed Voltage Architecture 509 11.20 Mixed Voltage Architecture - Single Power Supply 509 11.21 Mixed Voltage Architecture - Dual Power Supply 511 11.22 Mixed Signal Architecture 514 11.23 Digital and Analog Floor Plan - Placement of Analog Circuits 515 11.24 Mixed Signal Architecture - Digital, Analog, and RF Architecture 518 11.25 ESD Power Grid Design 519 11.26 I/O to Core Guard Rings 525 11.27 Within I/O Guard Rings 527 11.28 ESD-to-I/O Off-Chip Driver (OCD) Guard Ring 527 11.29 Guard Rings and Computer Aided Design (CAD) Methods 539 11.30 Summary and Closing Comments 541 References 541 12 ESD Digital Design 551 12.1 Fundamental Concepts of ESD Design 551 12.2 Concepts of ESD Digital Design 551 12.3 Device Response to External Events 552 12.4 Alternative Current Loops 553 12.5 Decoupling of Feedback Loops 554 12.6 Decoupling of Power Rails 554 12.7 Local and Global Distribution 554 12.8 Usage of Parasitic Elements 555 12.9 Unused Section of a Semiconductor Device, Circuit, or Chip Function 556 12.10 Unused Corners 556 12.11 Unused White Space 556 12.12 Impedance Matching Between Floating and Non-floating Networks 556 12.13 Unconnected Structures 557 12.14 Symmetry 557 12.15 Design Synthesis 557 12.16 ESD, Latchup, and Noise 559 12.17 Structures Under Bond Pads 574 12.18 Summary and Closing Comments 575 References 576 13 ESD Analog Design 583 13.1 Analog Design: Local Matching 583 13.2 Analog Design: Global Matching 583 13.3 Symmetry 584 13.4 Analog Design - Local Matching 584 13.5 Analog Design - Global Matching 584 13.6 Common Centroid Design 586 13.7 Common Centroid Arrays 586 13.8 Interdigitation Design 586 13.9 Common Centroid and Interdigitation Design 587 13.10 Dummy Resistor Layout 593 13.11 Thermoelectric Cancelation Layout 593 13.12 Electrostatic Shield 593 13.13 Interdigitated Resistors and ESD Parasitics 594 13.14 Capacitor Element Design 595 13.15 Inductor Element Design 596 13.16 ESD Failure in Inductors 597 13.17 Inductor Physical Variables 598 13.18 Inductor Element Design 599 13.19 Diode Design 599 13.20 Analog ESD Circuits 602 13.21 ESD MOSFETs 607 13.24 Analog Differential Pair Common Centroid Design Layout - Signal-pin to Signal-pin and Parasitic ESD Elements 620 13.25 Summary and Closing Comments 624 References 624 14 ESD RF Design 629 14.1 Fundamental Concepts of ESD Design 629 14.2 Fundamental Concepts of RF ESD Design 632 14.3 RF CMOS Input Circuits 637 14.4 RF CMOS Impedance Isolation LC Resonator ESD Networks 647 14.5 RF CMOS LC-diode Networks Experimental Results 648 14.6 RF CMOS LNA ESD Design - Low Resistance ESD Inductor and ESD Diode Clamping Elements in Π-configuration 650 14.7 RF CMOS T-coil Inductor ESD Input Network 653 14.8 RF CMOS Distributed ESD Networks 655 14.9 RF CMOS Distributed ESD-RF Networks 656 14.10 RF CMOS Distributed RF-ESD Networks Using Series Inductors and Dual-diode Shunts 656 14.11 RF CMOS Distributed RF-ESD Networks Using Series Inductors and MOSFET Parallel Shunts 659 14.12 RF CMOS Distributed ESD Networks - Transmission Lines and Co-planar Waveguides 661 14.13 RF CMOS - ESD and RF LDMOS Power Technology 663 14.14 Summary and Closing Comments 666 References 666 15 ESD Power Electronics Design 681 15.1 Reliability Technology Scaling and the Reliability Bathtub Curve 681 15.2 Input Circuitry 686 15.3 Summary and Closing Comments 702 References 702 16 ESD in Advanced CMOS 709 16.1 Interconnects and ESD 709 16.2 Aluminum Interconnects 710 16.3 Interconnects - Vias 714 16.4 Interconnects - Wiring 715 16.5 Junctions 719 16.6 Titanium Silicide 725 16.7 Shallow Trench Isolation 731 16.8 LOCOS-bound ESD Structures 734 16.9 LOCOS-bound p+/n-well Junction Diodes 734 16.10 LOCOS-bound n+ Junction Diodes 736 16.11 LOCOS-bound n-well/Substrate Diodes 737 16.12.…”

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