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“…Quotes This book teleports you into the seat of the chief architect on a data mesh project. - From the Foreword by Jean-Georges Perrin, PayPal A must-read for anyone who works in data. - Prukalpa Sankar, Co-Founder of Atlan Satisfies all those 'what', 'why', and 'how' questions. …”

“…Quotes This book teleports you into the seat of the chief architect on a data mesh project. - From the Foreword by Jean-Georges Perrin, PayPal A must-read for anyone who works in data. - Prukalpa Sankar, Co-Founder of Atlan Satisfies all those 'what', 'why', and 'how' questions. …”

Tabla de Contenidos: “…29 2.15 Conductors, Semiconductors, and Insulators 30 2.16 Static Dissipative Materials 30 2.17 ESD and Materials 31 2.18 Electrification and Coulomb's Law 31 2.19 Electromagnetism and Electrodynamics 33 2.20 Electrical Breakdown 33 2.21 Electro-Quasistatics and Magnetoquasistatics 36 2.22 Electrodynamics and Maxwell's Equations 36 2.23 Electrostatic Discharge (ESD) 36 2.24 Electromagnetic Compatibility (EMC) 37 2.25 Electromagnetic Interference (EMI) 37 2.26 Fundamentals of Manufacturing and Electrostatics 37 2.27 Materials, Tooling, Human Factors, and Electrostatic Discharge 38 2.28 Materials and Human-induced Electric Fields 39 2.29 Manufacturing Environment and Tooling 39 2.30 Manufacturing Equipment and ESD Manufacturing Problems 39 2.31 Manufacturing Materials 39 2.32 Measurement and Test Equipment 40 2.33 Manufacturing Testing for Compliance 41 2.34 Grounding and Bonding Systems 42 2.35 Work Surfaces 42 2.36 Wrist Straps 43 2.37 Constant Monitors 43 2.38 Footwear 43 2.39 Floors 44 2.40 Personnel Grounding with Garments 44 2.41 Garments 44 2.42 Air Ionization 44 2.43 Seating 45 2.44 Packaging and Shipping 46 2.45 Trays 46 2.46 ESD Identification 46 2.47 ESD Program Auditing 46 2.48 ESD On-Chip Protection 47 2.49 ESD, EOS, EMI, EMC, and Latchup 47 2.50 Manufacturing Electrical Overstress (EOS) 48 2.51 EMI 50 2.52 EMC 50 2.53 Summary and Closing Comments 50 References 50 3 ESD Standards 55 3.1 Factory - Flooring 55 3.2 Factory - Resistance Measurement of Materials 56 3.3 JEDEC 58 3.4 International Electro-Technical Commission (IEC) 59 3.5 IEEE 59 3.6 Department of Defense (DOD) 59 3.7 Military Standards 59 3.8 SAE 60 3.9 Summary and Closing Comments 60 Questions and Answers 60 References 61 4 ESD Testing 65 4.1 Electrostatic Discharge (ESD) Testing 65 4.2 ESD Models 65 4.3 HBM Test System 69 4.4 HBM Two-pin Test System 69 4.5 Machine Model (MM) 69 4.6 Small Charge Model (SCM) 70 4.7 Small Charge Model Source 71 4.8 CDM Pulse Waveform 72 4.9 HMM Equivalent Circuit 77 4.10 HMM Test Equipment 77 4.11 HMM Test Configuration 78 4.12 HMM Fixture Board 78 4.13 Transmission Line Pulse (TLP) 82 4.14 TLP Test Systems 84 4.15 IEC 61000-4-2 87 4.16 Equivalent Circuit 89 4.17 Test Equipment 89 4.18 Cable Discharge Event (CDE) 90 4.19 CDE Pulse Waveform 93 4.20 Equivalent Circuit 93 4.21 Commercial Test Systems 94 4.22 Systems Electromagnetic Interference (EMI) 95 4.23 Electromagnetic Compatibility (EMC) 95 4.24 Electrical Overstress (EOS) 95 4.25 Latchup 95 4.26 Electrical Overstress (EOS) 95 4.27 EOS Sources - Lightning 96 4.28 EOS Sources - Electromagnetic Pulse (EMP) 97 4.29 Electromagnetic Compatibility 97 4.30 Summary and Closing Comments 100 References 100 5 ESD Device Physics 117 5.1 Electro-thermal Instability 117 5.2 Stable System 118 5.3 Unstable System 118 5.4 Differential Relation of Voltage and Current 120 5.5 Time Constant Hierarchy 121 5.6 Thermal Physics Time Constants 121 5.7 Adiabatic, Thermal Diffusion Time Scale and Steady State 121 5.8 Electro-quasistatic and Magnetoquasistatics 122 5.9 Electrical Instability 124 5.10 Thermal Physics Time Constants 125 5.11 Adiabatic, Thermal Diffusion Time Scale and Steady State 126 5.12 Electrical Instability and Breakdown 126 5.13 Spatial Instability and Electro-thermal Current Constriction 127 5.14 Equipotential Surface 127 5.15 Heat Flow 128 5.16 Conservation of Heat 128 5.17 Electric Potential and Temperature Gradient 128 5.18 Electric Energy, Resistivity, and Thermal Conductivity 129 5.19 Breakdown 131 5.20 Electron Current Continuity Relationship 136 5.21 Air Breakdown and Peak Currents 138 5.22 Electro-thermal Instability 139 5.23 Mathematical Methods - Green's Function and Method of Images 141 5.24 Mathematical Methods - Green's Function and Method of Images 143 5.25 Mathematical Methods - Integral Transforms of the Heat Conduction Equation 148 5.26 Flux Potential Transfer Relations Matrix Methodology 152 5.27 Heat Equation Variable Conductivity 154 5.28 Mathematical Methods - Boltzmann Transformation 156 5.29 Mathematical Methods - The Duhamel Formulation 158 5.30 Spherical Source Tasca Model 160 5.31 Wunsch-Bell Model 163 5.32 The Smith and Littau Model 166 5.33 The Arkihpov-Astvatsaturyan-Godovosyn-Rudenko Model 168 5.34 The Vlasov-Sinkevitch Model 169 5.35 The Dwyer, Franklin and Campbell Model 169 5.36 Negative Differential Resistor and Resistor Ballasting 174 5.37 Ash Model - Nonlinear Failure Power Thresholds 176 5.38 Statistical Models for ESD Prediction 178 5.39 Summary and Closing Comments 180 References 180 6 ESD Events and Protection Circuits 189 6.1 Human Body Model (HBM) 189 6.2 Machine Model (MM) 191 6.3 Charged Device Model 193 6.4 Human Metal Model (HMM) 197 6.5 IEC 61000-4-2 History 204 6.6 IEC 61000-4-5 209 6.7 Cable Discharge Event (CDE) 213 6.8 CDM Scope 215 References 219 7 ESD Failure Mechanism 235 7.1 Tables of CMOS ESD Failure Mechanisms 235 7.2 LOCOS Isolation-Defined CMOS 235 7.3 LOCOS-bound Thick Oxide MOSFET 241 7.4 LOCOS-Bound Structures 242 7.5 Shallow Trench Isolation (STI) 245 7.6 STI Pull-down ESD Failure Mechanism 245 7.7 STI Pull-Down and Gate Wrap-Around 246 7.8 MOSFETs 247 7.9 LOCOS-bound Thick Oxide MOSFET 252 7.10 Bipolar Transistor Devices 254 7.11 Silicide Blocked N-diffusion Resistors 259 7.12 Silicon Germanium ESD Failure Mechanisms 259 7.13 Silicon Germanium Carbon ESD Failure Mechanisms 259 7.14 Gallium Arsenide Technology ESD Failure Mechanisms 260 7.15 Indium Gallium Arsenide ESD Failure Mechanisms 261 7.16 Micro Electromechanical (MEM) Systems 263 7.17 Micro-mirror Array Failures 265 7.18 EOS Bond Pad and Interconnect Failure 269 7.19 Summary and Closing Comments 272 References 273 8 ESD Design Synthesis 281 8.1 ESD Design Synthesis and Architecture Flow 281 8.2 ESD Design - the Signal Path and the Alternate Current Path 287 8.3 ESD Electrical Circuit and Schematic Architecture Concepts 289 8.4 The Ideal ESD Network 289 8.5 Mapping Semiconductor Chips and ESD Designs 293 8.6 Mapping across Semiconductor Fabricators 294 8.7 ESD Design Mapping across Technology Generations 295 8.8 ESD Networks, Sequencing, and Chip Architecture 306 8.9 ESD Layout and Floorplan-related Concepts 314 8.10 ESD Architecture and Floor-planning 323 8.11 Digital and Analog CMOS Architecture 347 8.12 Digital and Analog Floorplan - Placement of Analog Circuits 348 8.13 Mixed-signal Architecture - Digital, Analog, and RF Architecture 350 8.14 Summary and Closing Comments 351 Questions 351 References 352 9 On-chip ESD Protection Circuits - Input Circuitry 363 9.1 Receivers and ESD 363 9.2 Receivers and Receiver Delay Time 363 9.3 ESD Loading Effect on Receiver Performance 364 9.4 Receivers and HBM 365 9.5 Receivers and CDM 366 9.6 Receivers and Receiver Evolution 368 9.7 Receiver Circuits with Half-pass Transmission Gate 368 9.8 Receiver with Full-pass Transmission Gate 371 9.9 Receiver, Half-pass Transmission Gate, and Keeper Network 373 9.10 Receiver, Half-pass Transmission Gate, and the Modified Keeper Network 377 9.11 Receiver Circuits with Pseudo-zero VT Half-pass Transmission Gates 379 9.12 Receiver with Zero VT Transmission Gate 381 9.13 Receiver Circuits with Bleed Transistors 383 9.14 Receiver Circuits with Test Functions 384 9.15 Receiver with…”

“…Coaching coaches one-on-one and in small groups, she enjoys a front-row seat as remarkable agile coaches emerge and go on to entice the very best from the teams they coach. …”