Tabla de Contenidos: “…4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies…”