“…What you will learn Understand essential Rust concepts required to build blockchain Apply blockchain features such as nodes and p2 communication using Rust Understand and implement consensus in blockchain Build and deploy a dApp on Ethereum with the Foundry framework in Rust Develop and deploy a dApp on Solana and the NEAR protocol Build a custom blockchain using the Substrate framework by Polkadot Who this book is for This Rust programming book is for blockchain developers interested in building dApps on popular blockchains using Rust. …”

Tabla de Contenidos: “…. -- [S.l : s.n., s.a.] 15, [1] p., [2] en bl. ; Fol. Título sacado del comienzo del texto. …”

Tabla de Contenidos: “…. : s.n., s.a.] [2] p., [2] en bl. ; Fol. Fecha del documento: Gerona, 25 de dic. de 1780. …”

Tabla de Contenidos: “…. ; 4o (20 cm) Texto paralelo italiano y francés. Sign. : []\p2os, a10 cuadernos encuadernados. 2 cols. y 39 lín. …”

Accés lliure via BiPaDi

“…Por último, se aborda la interrelación del Reglamento (UE) de servicios digitales con el Reglamento plataforma a empresa (P2B) como necesario contrapeso de la Unión Europea al poder privado de las plataformas en línea, el estudio horizontal de las presentes normas digitales europeas con una singular visión desde el Reglamento de servicios digitales y la cooperación judicial penal con el entorno digital como escenario de los prestadores de servicios como coprotagonistas del Reglamento 2023/1543 sobre las órdenes europeas de producción y de conservación a efectos de prueba electrónica…”

Tabla de Contenidos: “….-- En Madrid : en la Imprenta Real de la Gazeta, 1766. [10] p., [2] en bl. ; Fol. Dada en Madrid el 04 de diciembre de 1760 Sign.: [ ]1, A5. …”

Tabla de Contenidos: “…Herramientas para el desarrollo de Redes sociales 3.3. Las redes P2P 4. Problemas de aplicación al proyecto Radio Friends 4.1. …”

Tabla de Contenidos: “….-- En Lisboa : [s.n.], 1745. [6], 40 p., [2] en bl. ; 4o. Sign. : ¶3, A-E4. Núm. de identificación: CCPB000233250-7…”

Tabla de Contenidos: “…4.5 Detecting Memory Objects Written by a Kernel -- 5 SnuCL extensions to OpenCL -- 6 Performance evaluation -- 6.1 Evaluation Methodology -- 6.2 Performance -- 6.2.1 Scalability on the medium-scale GPU cluster -- 6.2.2 Scalability on the large-scale CPU cluster -- 7 Conclusions -- Acknowledgments -- References -- Chapter 3: Thread communication and synchronization on massively parallel GPUs -- 1 Introduction -- 2 Coarse-Grained Communication and Synchronization -- 2.1 Global Barrier at the Kernel Level -- 2.2 Local Barrier at the Work-Group Level -- 2.3 Implicit Barrier at the Wavefront Level -- 3 Built-In Atomic Functions on Regular Variables -- 4 Fine-Grained Communication and Synchronization -- 4.1 Memory Consistency Model -- 4.1.1 Sequential consistency -- 4.1.2 Relaxed consistency -- 4.2 The OpenCL 2.0 Memory Model -- 4.2.1 Relationships between two memory operations -- 4.2.2 Special atomic operations and stand-alone memory fence -- 4.2.3 Release and acquire semantics -- 4.2.4 Memory order parameters -- 4.2.5 Memory scope parameters -- 5 Conclusion and Future Research Direction -- References -- Chapter 4: Software-level task scheduling on GPUs -- 1 Introduction, Problem Statement, and Context -- 2 Nondeterministic behaviors caused by the hardware -- 2.1 P1: Greedy -- 2.2 P2: Not Round-Robin -- 2.3 P3: Nondeterministic Across Runs -- 2.4 P4: Oblivious to Nonuniform Data Sharing -- 2.5 P5: Serializing Multikernel Co-Runs -- 3 SM-centric transformation -- 3.1 Core Ideas -- 3.1.1 SM-centric task selection -- Correctness issues -- 3.1.2 Filling-retreating scheme -- 3.2 Implementation -- 3.2.1 Details -- 4 Scheduling-enabled optimizations -- 4.1 Parallelism Control -- 4.2 Affinity-Based Scheduling -- 4.2.1 Evaluation -- 4.3 SM Partitioning for Multi-Kernel Co-Runs -- 4.3.1 Evaluation -- 5 Other scheduling work on GPUs -- 5.1 Software Approaches…”

Tabla de Contenidos: “…Front Cover -- Three-Dimensional Integrated Circuit Design -- Copyright Page -- Dedication -- Contents -- List of Figures -- About the Authors -- Preface to the Second Edition -- Preface to the First Edition -- Acknowledgments -- Organization of the Book -- 1 Introduction -- 1.1 Interconnect Issues in Integrated Systems -- 1.2 Three-Dimensional or Vertical Integration -- 1.2.1 Opportunities for Three-Dimensional Integration -- 1.2.2 Challenges of Three-Dimensional Integration -- 1.2.2.1 Technological/manufacturing limitations -- 1.2.2.2 Testing -- 1.2.2.3 Global interconnect design -- 1.2.2.4 Thermal issues -- 1.2.2.5 CAD algorithms and tools -- 1.3 Book Organization -- 2 Manufacturing of Three-Dimensional Packaged Systems -- 2.1 Stacking Methods for Transistors, Circuits, and Dies -- 2.1.1 System-in-Package -- 2.1.2 Transistor and Circuit Level Stacking -- 2.2 System-on-Package -- 2.3 Technologies for System-in-Package -- 2.3.1 Wire Bonded System-in-Package -- 2.3.2 Peripheral Vertical Interconnects -- 2.3.3 Area Array Vertical Interconnects -- 2.3.4 Metalizing the Walls of an SiP -- 2.4 Technologies for 2.5-D Integration -- 2.4.1 Interposer Materials -- 2.4.2 Metallization Processes -- 2.4.3 Vertical Interconnects -- 2.5 Summary -- 3 Manufacturing Technologies for Three-Dimensional Integrated Circuits -- 3.1 Monolithic Three-Dimensional ICs -- 3.1.1 Laser Crystallization -- 3.1.2 Seed Crystallization -- 3.1.3 Double-Gate Metal Oxide Semiconductor Field Effect Transistors for Stacked Three-Dimensional ICs -- 3.1.4 Molecular Bonding -- 3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via -- 3.2.1 Wafer Level Integration -- 3.2.2 Die-to-Die Integration -- 3.2.3 Bonding of Three-Dimensional ICs -- 3.3 Contactless Three-Dimensional ICs -- 3.3.1 Capacitively Coupled Three-Dimensional ICs…”

Tabla de Contenidos: “…Preface xv -- Acknowledgments xxi -- Contributors xxiii -- PART I CDN AND MEDIA STREAMING BASICS 1 -- 1 CLOUD-BASED CONTENT DELIVERY AND STREAMING 3 /Mukaddim Pathan -- 1.1 Introduction 3 -- 1.2 CDN Overview 5 -- 1.3 Workings of a CDN 10 -- 1.4 CDN Trends 21 -- 1.5 Research Issues 28 -- 1.6 Conclusion 29 -- References 29 -- 2 LIVE STREAMING ECOSYSTEMS 33 /Dom Robinson -- 2.1 Introduction 33 -- 2.2 Live Streaming Pre-Evolution 34 -- 2.3 Live, Linear, Nonlinear 35 -- 2.4 Media Streaming 37 -- 2.5 Related Network Models 38 -- 2.6 Streaming Protocol Success 43 -- 2.7 Platform Divergence and Codec Convergence 44 -- 2.8 Adaptive Bitrate (ABR) Streaming 45 -- 2.9 Internet Radio and HTTP 48 -- 2.10 Conclusion 48 -- References 49 -- 3 PRACTICAL SYSTEMS FOR LIVE STREAMING 51 /Dom Robinson -- 3.1 Introduction 51 -- 3.2 Common Concepts in Live Streaming 52 -- 3.3 The Practicals 56 -- 3.4 Conclusion 69 -- References 70 -- 4 EFFICIENCY OF CACHING AND CONTENT DELIVERY IN BROADBAND ACCESS NETWORKS 71 /Gerhard Haslinger -- 4.1 Introduction 71 -- 4.2 Options and Properties for Web Caching 73 -- 4.3 Zipf Laws for Requests to Popular Content 75 -- 4.4 Efficiency and Performance Modeling for Caches 76 -- 4.5 Effect of Replacement Strategies on Cache Hit Rates 78 -- 4.6 Replacement Methods Based on Request Statistics 81 -- 4.7 Global CDN and P2P Overlays for Content Delivery 84 -- 4.8 Summary and Conclusion 86 -- Acknowledgments 87 -- References 87 -- 5 ANYCAST REQUEST ROUTING FOR CONTENT DELIVERY NETWORKS 91 /Hussein A. …”

Tabla de Contenidos: “…En h. 2 se hace referencia al "año proximo passado de 1730" Sign. : [A]-P2 Port. con orla tip. Catedral de Granada-Concursos y oposiciones-S. …”

Tabla de Contenidos: “…. : s.n., s.a.]. [2] p., [2] en bl. ; Fol. Se ha respetado la puntuación original. …”

Tabla de Contenidos: “….) -- 3 INTERCONEXIÓN DE REDES -- 3.1 CONCEPTOS BÁSICOS SOBRE REDES PÚBLICAS -- 3.1.1 LÍNEAS DEDICADAS -- 3.1.3 DIAL UP -- 3.1.4 COMUNICACIONES VÍA SATÉLITE -- 3.2 REDES DEFINIDAS POR TOPOLOGÍA -- 3.2.1 TOPOLOGÍA EN BUS -- 3.2.2 TOPOLOGÍA EN ANILLO -- 3.2.3 TOPOLOGÍA EN ESTRELLA -- 3.2.4 TOPOLOGÍA PUNTO A PUNTO -- 3.2.5 TOPOLOGÍA PUNTO MULTIPUNTO (HUB AND SPOKE TOPOLOGY) -- 3.2.6 TOPOLOGÍA EN MALLA COMPLETA (FULL-MESH TOPOLOGY) -- 3.2.7 TOPOLOGÍA EN MALLA PARCIAL (PARTIAL-MESHED TOPOLOGY) -- 3.3 REDES SEGÚN SU EXTENSIÓN GEOGRÁFICA -- 3.3.1 REDES DE ÁREA LOCAL (LAN) -- 3.3.2 REDES DE ÁREA AMPLIA (WAN) -- 3.3.3 REDES CAMPUS (CAN) -- 3.3.4 REDES DE ÁREA METROPOLITANA (MAN) -- 3.3.5 REDES DE ÁREA PERSONAL (PAN) -- 3.4 REDES SEGÚN LA UBICACIÓN DE LOS RECURSOS -- 3.4.1 REDES CLIENTE-SERVIDOR -- 3.4.2 REDES PEER-TO-PEER (P2P) -- 4 MODELOS DE REFERENCIA -- 4.1 EL MODELO OSI -- 4.1.1 CAPA FÍSICA (CAPA 1) -- 4.1.2 CAPA DE ENLACE DE DATOS (CAPA 2) -- 4.1.3 CAPA DE RED (CAPA 3) -- 4.1.4 CAPA DE TRANSPORTE (CAPA 4) -- 4.1.5 CAPA DE SESIÓN (CAPA 5) -- 4.1.6 CAPA DE PRESENTACIÓN (CAPA 6) -- 4.1.7 CAPA DE APLICACIÓN (CAPA 7) -- 4.2 INTRODUCCIÓN AL ENCAPSULAMIENTO -- 4.3 EL MODELO TCP/IP -- 4.3.1 LA CAPA INTERFAZ DE RED -- 4.3.2 LA CAPA INTERNET…”

Tabla de Contenidos: “…Cover -- Dedication -- Contents -- Preface to the First Edition -- Preface -- Acknowledgements -- Chapter 1 : Introduction -- Chapter Objectives -- 1.1 Introduction -- 1.2 Microprocessor -- 1.2.1 Microprocessor-Based System -- 1.3 Microcontroller -- 1.3.1 General Architecture -- 1.3.2 Software Protection in Microcontrollers -- 1.3.3 Brief History of Intel Microcontrollers -- 1.4 MCS-51 Family -- 1.4.1 Princeton and Harvard Architectures -- 1.4.2 Comparison Between 8085 and MCS-51 -- 1.5 Power Management -- 1.6 Microcontroller Packaging -- 1.6.1 Plastic Dual-Inline Package (PDIP) -- 1.6.2 Quad Flat Package (QFP) -- 1.6.3 Plastic-Leaded Chip Carrier (PLCC) -- 1.6.4 Plastic Quad Flat Pack (PQFP) -- 1.6.5 Thin Quad Flat Pack (TQFP) -- 1.7 Future Trend -- Summary -- Points to Remember -- Review Questions -- Evaluate Yourself -- Search for Answers -- Think and Solve -- Chapter 2 : General Architecture -- Chapter Objectives -- 2.1 External Features -- 2.2 Pins and Signals -- 2.3 Internal Architecture -- 2.4 Program Memory Organization -- 2.4.1 Pipeline Architecture -- 2.4.2 Program Lock Bits -- 2.5 Data Memory Organization -- 2.5.1 Register Banks -- 2.5.2 Bit-Addressable Area -- 2.5.3 Scratch-Pad Area -- 2.6 System Clock -- 2.7 Reset -- 2.8 How to Program 8051 -- 2.8.1 Overview of Programming -- 2.8.2 Editor -- 2.8.3 Assembler -- 2.8.4 Burning the Chip -- 2.8.5 IDE -- Summary -- Points to Remember -- Review Questions -- Evaluate Yourself -- Search for Answers -- Think and Solve -- Chapter 3 : I/O Ports and Special Function Registers -- Chapter Objectives -- 3.1 Introduction -- 3.2 SFR Map -- 3.3 SFR Functions -- 3.4 Processor Status Word -- 3.4.1 Comparison with 8085 Flags -- 3.5 Accumulator (Register A) -- 3.6 Register B -- 3.7 Stack Pointer -- 3.8 Port Registers (P0, P1, P2 and P3) -- 3.8.1 Comparing 8255 PPI with MCS-51 Ports…”