Tabla de Contenidos: “…-- PostgreSQL 10.x and NoSQL -- PostgreSQL as HUB -- PostgreSQL tools -- PostgreSQL contrib -- Finding contrib modules on your system -- Installing a contrib module from source -- Using a contrib module -- pgFoundry -- PGXN -- Additional PostgreSQL-related software -- PostgreSQL application scaling life cycle -- Performance tuning as a practice -- Summary -- Chapter 2: Database Hardware -- Balancing hardware spending -- CPUs -- Memory -- Disks -- RAID -- Drive error handling -- Hard drive reliability studies -- Drive firmware and RAID -- SSDs -- Disk controllers -- Hardware and software RAID -- Recommended disk controllers -- Attached storage - SAN and NAS -- Reliable controller and disk setup -- Write-back caches -- Sources of write-back caching -- Disk controller monitoring -- Disabling drive write caches -- Performance impact of write-through caching -- Summary -- Chapter 3: Database Hardware Benchmarking -- CPU and memory benchmarking -- Memtest86+ -- STREAM memory testing -- STREAM and Intel versus AMD -- CPU benchmarking -- Sources of slow memory and processors -- Physical disk performance -- Random access and input/outputs per second -- Sequential access and ZCAV -- Short stroking -- Commit rate -- PostgreSQL test_fsync -- INSERT rate -- Windows commit rate -- Disk benchmarking tools -- HD Tune -- Short stroking tests -- IOPS -- Unpredictable performance and Windows…”

Tabla de Contenidos: “…Tiva C Launchpad -- Ultrasonic sensor -- Ultrasonic sensor -- OpenNI depth sensor -- Intel NUC -- Interfacing sensors and motors with the Launchpad -- Programming the Tiva C Launchpad -- Interfacing robot hardware with ROS -- Running Chefbot ROS driver nodes -- Gmapping and localization in Chefbot -- Questions -- Summary -- 10. …”

Tabla de Contenidos: “…. -- Initiatives to Strengthen Project Management Capacity at Hitachi -- References -- 3.5 Farm Credit Mid-America Best Practices -- Farm Credit Mid-America Introduction -- Farm Credit Mid-America's Starting Point -- Adopting Project Management Best Practices -- References -- 3.6 NCS Integrated Delivery Methods (IDM) &amp -- Project Management Method (PMM) -- NCS Integrated Delivery Methods (IDM) -- NCS Project Management Method (PMM) -- Change Control Process -- 3.7 Managing Change Within Research and Development at Business Area Networks, Ericsson -- About Ericsson -- 3.8 Intel Corporation and "Map Days" -- 3.9 Apple Computer and Cell Phones -- 3.10 The Light at the End of the Tunnel -- 3.11 Managing Assumptions -- 3.12 Project Governance -- 3.13 Seven Fallacies That Delay Project Management Maturity -- 3.14 Motorola -- 3.15 Texas Instruments -- 3.16 Naviair: On Time-On Budget -- How to Make Big and Complex Programs a Success -- Organize and Report -- Communicate Everywhere -- Summary -- 3.17 Avalon Power and Light -- 3.18 Roadway Express -- 3.19 Kombs Engineering -- 3.20 Williams Machine Tool Company -- 4 Project Management Methodologies -- 4.0 Introduction -- 4.1 Excellence Defined -- 4.2 Recognizing the Need for Methodology Development -- Organizing -- Planning -- Managing -- 4.3 Enterprise Project Management Methodologies -- Light Methodologies -- Heavy Methodologies…”

Tabla de Contenidos: “…-- Let's Try It Out -- Items to Consider -- Other AG Enhancements -- AG Reliability and Supportability -- Distributed Availability Group (DAG) Enhancements -- Recovery Enhancements -- Accelerated Database Recovery (ADR) Enhancements -- Parallel Redo Enhancements -- Backup/Restore Enhancements -- Cross-Platform SNAPSHOT Backup -- How Does It Work? -- Intel QuickAssist (QAT) Backup Compression -- Backup Metadata -- Multi-write Replication -- Other Engine "Stuff" -- XML Compression -- In-Memory OLTP Memory Management -- Auto-drop Statistics -- Resumable Add Table Constraints -- New Wait Types -- New Extended Events -- An Industry-Proven Engine -- Chapter 7: Data Virtualization and Object Storage -- Data Virtualization in SQL Server 2022 -- REST, Azure Storage, and S3…”

Tabla de Contenidos: “…Specifying Server configuration settings for LDAP -- A.0.1 Adding portal administrators to the Domino Directory -- Updating the Access Control List of the Domino Directory -- Configuring WebSphere Portal for Domino Directory -- Security is enabled -- Verifying LDAP -- WebSphere Portal Server hardware requirements for Linux Intel systems -- Appendix B. Configuring Internet Cluster Manager -- Internet Cluster Manager -- Configuring the ICM -- Setting up a separate IP address for the ICM -- Appendix C. …”

Tabla de Contenidos: “…Front Cover -- Multicore and GPU Programming: An Integrated Approach -- Copyright -- Dedication -- Contents -- List of Tables -- Preface -- What Is in This Book -- Using This Book as a Textbook -- Software and Hardware Requirements -- Sample Code -- Chapter 1: Introduction -- 1.1 The era of multicore machines -- 1.2 A taxonomy of parallel machines -- 1.3 A glimpse of contemporary computing machines -- 1.3.1 The cell BE processor -- 1.3.2 Nvidia's Kepler -- 1.3.3 AMD's APUs -- 1.3.4 Multicore to many-core: tilera's TILE-Gx8072 and intel's xeon phi -- 1.4 Performance metrics -- 1.5 Predicting and measuring parallel program performance -- 1.5.1 Amdahl's law -- 1.5.2 Gustafson-barsis's rebuttal -- Exercises -- Chapter 2: Multicore and parallel program design -- 2.1 Introduction -- 2.2 The PCAM methodology -- 2.3 Decomposition patterns -- 2.3.1 Task parallelism -- 2.3.2 Divide-and-conquer decomposition -- 2.3.3 Geometric decomposition -- 2.3.4 Recursive data decomposition -- 2.3.5 Pipeline decomposition -- 2.3.6 Event-based coordination decomposition -- 2.4 Program structure patterns -- 2.4.1 Single-program, multiple-data -- 2.4.2 Multiple-program, multiple-data -- 2.4.3 Master-worker -- 2.4.4 Map-reduce -- 2.4.5 Fork/join -- 2.4.6 Loop parallelism -- 2.5 Matching decomposition patterns with program structure patterns -- Exercises -- Chapter 3: Shared-memory programming: threads -- 3.1 Introduction -- 3.2 Threads -- 3.2.1 What is a thread? …”

Tabla de Contenidos: “…Tivoli Configuration Manager fundamentals and installation -- 3.1 IBM Tivoli Configuration Manager fundamentals -- 3.1.1 Tivoli Configuration Manager components and services -- 3.2 Creating a deployment plan for Tivoli Configuration Manager -- 3.3 How to deploy Tivoli Configuration Manager components -- 3.3.1 Distributed Configuration Manager components -- 3.3.2 TMR server configuration -- 3.3.3 Components for managed nodes -- 3.3.4 Components for gateways -- 3.3.5 Components for endpoints -- 3.4 Required roles for installation -- 3.5 RDBMS considerations -- 3.6 RIM considerations -- 3.7 General pre-install checks, hints, and tips -- 3.7.1 UNIX -- 3.7.2 Windows Systems on Intel® 486 or Pentium® systems -- 3.8 Installation methods -- 3.9 Overview of Integrated Install -- 3.10 Server Install -- 3.10.1 Typical Server Install -- 3.10.2 Custom Server Install -- 3.10.3 Starting the installation programs -- 3.11 Desktop Install -- 3.11.1 Starting the installation program -- 3.12 Web Gateway Install -- 3.12.1 Web Gateway prerequisites -- 3.12.2 Starting the installation program -- 3.12.3 Multiple endpoints installation -- 3.13 Uninstallation of IBM Tivoli Configuration Manager -- Chapter 4. …”

Tabla de Contenidos: “…8.6.5 Implementation of Threaded Code on Motorola 68000 -- 8.6.6 Implementation of Threaded Code on Intel x86 Machines -- 8.7 SECD and WAM -- 8.8 Grammar and IR Generation for miniC -- 8.8.1 Expressions -- 8.8.2 Assignments -- 8.8.3 Statements -- 8.8.4 IF-THEN and IF-THEN-ELSE -- 8.8.5 WHILE-DO -- 8.8.6 Variable Declarations -- 8.8.7 Function Definitions -- 8.8.8 Function Calls -- 8.8.9 Utility Functions Used -- 8.9 Real-life: Intermediate Codes of GNU gcc -- 8.9.1 Example GCC Intermediate Code -- Exercises -- Further Reading -- Glossary -- Chapter 9: Code Generation and Machine-dependent Optimization -- 9.1 Our Concerns in Code Generation -- 9.1.1 Input Intermediate Representation (IR) -- 9.1.2 Nature of Target Language -- 9.1.3 Selection of Alternatives from Instruction Set -- 9.1.4 Allocation of CPU Registers -- 9.1.5 Order of Evaluation Sequence -- 9.2 The Target Language -- 9.2.1 x86 Assembly Language in GAS Syntax -- 9.3 Data Structures -- 9.3.1 Vectors and Arrays -- 9.3.2 Vectors -- 9.3.3 Arrays -- 9.4 Control Constructs -- 9.5 Procedures and Function Calls -- 9.5.1 Function Prologue and Epilogue -- 9.5.2 Saving Registers -- 9.5.3 A Test for C Linkage -- 9.6 The Target Operating Environment -- 9.6.1 Memory Management -- 9.6.2 CPU Register Usage -- 9.6.3 Activation Record (AR) -- 9.7 Code Optimization -- 9.8 Machine-dependent Optimization -- 9.8.1 Register Allocation -- 9.8.2 Instruction Rescheduling: Use of Parallelism in Instruction Execution -- 9.9 Converting the 4-Tuple and RPN into Assembly Code -- 9.9.1 Conversion of 4-Tuple to Assembly Code -- 9.9.2 Conversion of RPN to Assembly Code -- Exercises -- Further Reading -- Glossary -- Chapter 10: Code Optimization -- 10.1 Basic Blocks -- 10.1.1 Formal Algorithm to Delineate BBs -- 10.1.2 Reference and Define Information -- 10.1.3 Loops in Flow-graphs -- 10.1.4 Example Implementation - miniC…”

Tabla de Contenidos: “…2.4.5 Printers -- 2.4.6 Telecommunications Equipment -- 2.4.7 Digital Cameras -- 2.4.8 Character Codes -- 2.5 SUMMARY -- 3 THE DIGITAL LOGIC LEVEL -- 3.1 GATES AND BOOLEAN ALGEBRA -- 3.1.1 Gates -- 3.1.2 Boolean Algebra -- 3.1.3 Implementation of Boolean Functions -- 3.1.4 Circuit Equivalence -- 3.2 BASIC DIGITAL LOGIC CIRCUITS -- 3.2.1 Integrated Circuits -- 3.2.2 Combinational Circuits -- 3.2.3 Arithmetic Circuits -- 3.2.4 Clocks -- 3.3 MEMORY -- 3.3.1 Latches -- 3.3.2 Flip-Flops -- 3.3.3 Registers -- 3.3.4 Memory Organization -- 3.3.5 Memory Chips -- 3.3.6 RAMs and ROMs -- 3.4 CPU CHIPS AND BUSES -- 3.4.1 CPU Chips -- 3.4.2 Computer Buses -- 3.4.3 Bus Width -- 3.4.4 Bus Clocking -- 3.4.5 Bus Arbitration -- 3.4.6 Bus Operations -- 3.5 EXAMPLE CPU CHIPS -- 3.5.1 The Intel Core i7 -- 3.5.2 The Texas Instruments OMAP4430 System-on-a-Chip -- 3.5.3 The Atmel ATmega168 Microcontroller -- 3.6 EXAMPLE BUSES -- 3.6.1 The PCI Bus -- 3.6.2 PCI Express -- 3.6.3 The Universal Serial Bus -- 3.7 INTERFACING -- 3.7.1 I/O Interfaces -- 3.7.2 Address Decoding -- 3.8 SUMMARY -- 4 THE MICROARCHITECTURE LEVEL -- 4.1 AN EXAMPLE MICROARCHITECTURE -- 4.1.1 The Data Path -- 4.1.2 Microinstructions -- 4.1.3 Microinstruction Control: The Mic-1 -- 4.2 AN EXAMPLE ISA: IJVM -- 4.2.1 Stacks -- 4.2.2 The IJVM Memory Model -- 4.2.3 The IJVM Instruction Set -- 4.2.4 Compiling Java to IJVM -- 4.3 AN EXAMPLE IMPLEMENTATION -- 4.3.1 Microinstructions and Notation -- 4.3.2 Implementation of IJVM Using the Mic-1 -- 4.4 DESIGN OF THE MICROARCHITECTURE LEVEL -- 4.4.1 Speed versus Cost -- 4.4.2 Reducing the Execution Path Length -- 4.4.3 A Design with Prefetching: The Mic-2 -- 4.4.4 A Pipelined Design: The Mic-3 -- 4.4.5 A Seven-Stage Pipeline: The Mic-4 -- 4.5 IMPROVING PERFORMANCE -- 4.5.1 Cache Memory -- 4.5.2 Branch Prediction -- 4.5.3 Out-of-Order Execution and Register Renaming…”

Tabla de Contenidos: “…-- 2.1 Server als Definitionssache -- 2.2 Von Hosts und Servern -- 2.3 Warum ein PC kein Server ist -- 2.4 Bauformen von Servern -- 2.5 Alles eine Frage der Höheneinheit -- 2.6 KVMs -- 2.7 Fragen zu diesem Kapitel -- Kapitel 3: Serverhardware -- 3.1 Die Architektur von Servern -- 3.1.1 Alt, aber noch vorhanden: PCI -- 3.1.2 PCI-X -- 3.1.3 PCI-Express -- 3.1.4 Die Weiterentwicklungen bei Intel -- 3.1.5 Die Bussysteme im Vergleich -- 3.1.6 Chipsets im Vergleich -- 3.2 Prozessoren für Server -- 3.2.1 Technische Funktion der CPU -- 3.2.2 Hardwarevirtualisierung via Prozessor -- 3.2.3 Mehrkernprozessoren -- 3.2.4 Cache-Speicher (Pufferspeicher) -- 3.3 Der Arbeitsspeicher -- 3.3.1 Unterschiedliche Funktionsweisen -- 3.3.2 Aufbau von RAM-Bausteinen -- 3.3.3 Fehlerbehandlung -- 3.3.4 Aktuelle RAM-Typen -- 3.3.5 Single Channel, Dual Channel, Quad Channel -- 3.3.6 Bauformen -- 3.4 Kühlung von Servern -- 3.4.1 Wärmeleitpaste -- 3.4.2 Lüfter -- 3.4.3 Kühlkörper -- 3.4.4 Wasserkühlung -- 3.5 Hot-Plug-Architekturen -- 3.6 BIOS in ROM? …”

Tabla de Contenidos: “…13.2.2 用profvis 性 分析 -- 13.2.3 理 代码为什么会慢 -- 13.3 提 代码性 -- 13.3.1 使用内置函数 -- 13.3.2 使用向 化 -- 13.3.3 使用字 码编 器 -- 13.3.4 使用由Intel MKL 支持的R -- 13.3.5 使用并 算 -- 13.3.6 使用Rcpp -- 13.4 小结 -- 第14章 网 爬虫 -- 14.1 查 网 内容 -- 14.2 使用 CSS 择器从网 中提取数据 -- 14.3 使用XPath 择器 -- 14.4 分析HTML 代码并提取数据 -- 14.5 小结 -- 第15章 效率提升 -- 15.1 编写R Markdown 文档 -- 15.1.1 了 markdown -- 15.1.2 将R整合到markdown中 -- 15.1.3 嵌入 格和图 -- 15.2 创建交互式应用程序 -- 15.2.1 创建shiny 应用程序 -- 15.2.2 使用shinydashboard -- 15.3 小结 -- 录 术…”

Tabla de Contenidos: “…La recherche-développement chez Intel -- Graphique 3.6. Investissements en capital-risque privé -- Encadré 3.2. …”

Tabla de Contenidos: “…-- 2.1 Server als Definitionssache -- 2.2 Von Hosts und Servern -- 2.3 Warum ein PC kein Server ist -- Kapazität‌: -- Ausbaubarkeit‌: -- Physische Sicherheit‌: -- Eignung für den Dauerbetrieb‌: -- Lebenszeit von Systemen und Verfügbarkeit der Ersatzteile: -- 2.4 Bauformen von Servern -- 2.5 Alles eine Frage der Höheneinheit -- 2.6 KVMs -- 2.7 Out-of-Band-Management -- 2.8 Fragen zu diesem Kapitel -- Kapitel 3: Serverhardware -- 3.1 Die Architektur von Servern -- 3.1.1 Etwas Historie zu Beginn: PCI -- 3.1.2 PCI-X‌ -- 3.1.3 PCI Express -- 3.1.4 Die Weiterentwicklungen bei Intel -- 3.1.5 Die Bussysteme im Vergleich -- 3.1.6 Chipsets im Vergleich -- 3.2 Prozessoren für Server -- 3.2.1 Technische Funktion der CPU -- 3.2.2 Hardware-Virtualisierung via Prozessor -- 3.2.3 Mehrkernprozessoren -- 3.2.4 Cache-Speicher (Pufferspeicher) -- 3.3 Der Arbeitsspeicher -- 3.3.1 Unterschiedliche Funktionsweisen -- 3.3.2 Aufbau von RAM-Bausteinen -- 3.3.3 Fehlerbehandlung -- 3.3.4 Aktuelle RAM-Typen -- 3.3.5 Single Channel, Dual Channel, Quad Channel -- 3.3.6 Bauformen -- 3.4 Kühlung von Servern -- 3.4.1 Wärmeleitpaste -- 3.4.2 Lüfter -- 3.4.3 Kühlkörper -- 3.4.4 Wasserkühlung -- 3.5 Hot-Plug-Architekturen -- 3.6 Die wichtigsten Übertragungsmedien -- 3.6.1 Twisted-Pair-Kabel -- 3.6.2 Unshielded Twisted Pair -- 3.6.3 Shielded Twisted Pair‌ -- 3.6.4 Koaxialkabel -- 3.6.5 Lichtwellenleiter‌ -- 3.7 Netzwerkkarten -- 3.7.1 Wake on LAN‌ -- 3.7.2 Adapter Teaming -- 3.7.3 Medienkonverter -- 3.8 Virtuelle Netzwerkkomponenten -- 3.9 BIOS in ROM? …”

“…Prior to creating KAMIND, Matt worked for Intel Corporation for 17 years managing engineering development, IT projects, and working with the Intel security group. …”

Tabla de Contenidos: “…OMEC, Towards Cloud Native and 5G Service-Based Architecture 184 -- 7.4.1 High Volume ServerśÖ Software and Hardware Optimization for Packet Processing 188 -- 7.4.1.1 Data Plane Development Kit 188 -- 7.4.1.2 Flow Classification Bottleneck 190 -- 7.4.1.3 Cuckoo Hashing for Efficient Table Utilization 190 -- 7.4.1.4 Intel Resource Director Technology 192 -- 7.5 Part III: Software-Defined Disaggregated RAN 193 -- 7.5.1 RAN Disaggregation 193 -- 7.5.2 Software-Defined RAN Control 194 -- 7.6 Part IV: White-Box Solutions for Compute, Storage, Access, and Networking 197 -- 7.7 Part V: Edge Cloud Deployment Options 200 -- 7.8 Part VI: Edge Cloud and Network Slicing 204 -- 7.9 Summary 207 -- Acknowledgments 207 -- References 208 -- Part V 5G Verticals ́ô Key Vertical Applications 211 -- 8 Connected Aerials 213 /Feng Xue, Shu-ping Yeh, Jingwen Bai, and Shilpa Talwar -- 8.1 Introduction 213 -- 8.2 General Requirements and Challenges for Supporting UAVs over a Cellular Network 215 -- 8.3 Summary on Current Drone Regulations 217 -- 8.4 Review of Aerial Communication R&D Activities in General 217.…”

Tabla de Contenidos: “…ITSO lab hardware descriptions -- WebSphere Voice Server on Intel Servers -- Server 1: IBM ^ xSeries 206: Machine Type/Model 8482-2RU -- Server 2: IBM ^ xSeries 230: Machine Type/Model 8658-61Y -- Server 3: IBM ^ xSeries 345: Machine Type/Model 8670-M1X -- IVR 1: WebSphere Voice Response on IBM ^ pSeries -- IVR 2: Avaya Interactive Response (Avaya IR) V1.3 on a Sun Workstation -- IVR 3: Cisco Internet Operating System (IOS) on a Cisco AS5400 Series Universal Gateway…”