Tabla de Contenidos: “…Chapter 10: RRAM Device and CircuitChapter 11: Phase-Change Random Access Memory; Chapter 12: Nano-DRAM Technology for Data Storage Application; Chapter 13: Ferroelectric Memory; Chapter 14: Nanomagnetic and Hybrid Information Storage; Back Cover…”

Tabla de Contenidos: “…Chapter 6: Registers and Register Transfers -- Registers and Load Enable -- Register with Parallel Load -- Register Transfers -- Register Transfer Operations -- Register Transfers in VHDL and Verilog -- Microoperations -- Arithmetic Microoperations -- Logic Microoperations -- Shift Microoperations -- Microoperations on a Single Register -- Multiplexer-Based Transfers -- Shift Registers -- Ripple Counter -- Synchronous Binary Counters -- Other Counters -- Register-Cell Design -- Multiplexer and Bus-Based Transfers for Multiple Registers -- High-Impedance Outputs -- Three-State Bus -- Serial Transfer and Microoperations -- Serial Addition -- Control of Register Transfers -- Design Procedure -- HDL Representation for Shift Registers and Counters-VHDL -- HDL Representation for Shift Registers and Counters-Verilog -- Microprogrammed Control -- Chapter Summary -- References -- Problems -- Chapter 7: Memory Basics -- Memory Definitions -- Random-Access Memory -- Write and Read Operations -- Timing Waveforms -- Properties of Memory -- SRAM Integrated Circuits -- Coincident Selection -- Array of SRAM ICs -- DRAM ICs -- DRAM Cell -- DRAM Bit Slice -- DRAM Types -- Synchronous DRAM (SDRAM) -- Double-Data-Rate SDRAM (DDR SDRAM) -- RAMBUS® DRAM (RDRAM) -- Arrays of Dynamic RAM ICs -- Chapter Summary -- References -- Problems -- Chapter 8: Computer Design Basics -- Introduction -- Datapaths -- The Arithmetic/Logic Unit -- Arithmetic Circuit -- Logic Circuit -- Arithmetic/Logic Unit -- The Shifter -- Barrel Shifter -- Datapath Representation -- The Control Word -- A Simple Computer Architecture -- Instruction Set Architecture -- Storage Resources -- Instruction Formats -- Instruction Specifications -- Single-Cycle Hardwired Control -- Instruction Decoder -- Sample Instructions and Program -- Single-Cycle Computer Issues -- Multiple-Cycle Hardwired Control…”

Tabla de Contenidos: “…Front Cover; Contents; Preface; Editors; Contributors; Chapter 1: Introduction to the Effects of Radiation on Electronic Devices; Chapter 2: Monte Carlo Simulation of Radiation Effects; Chapter 3: A Complete Guide to Multiple Upsets in SRAMs Processed in Decananometric CMOS Technologies; Chapter 4: Radiation Effects in DRAMs; Chapter 5: Radiation Effects in Flash Memories; Chapter 6: Microprocessor Radiation Effects; Chapter 7: Soft-Error Hardened Latch and Flip-Flop Design; Chapter 8: Assuring Robust Triple-Modular Redundancy Protected Circuits in SRAM-Based FPGAs…”

Enlace del recurso

Trailer en espaæol

Tabla de Contenidos: “…Latina -- Taiwán es el tercer proveedor mundial de memoria DRAM -- Nuevo software podría poner fin al correo basura -- La FIFA en Internet registró 79 millones de visitas en un día -- Manifestación contra Echelon -- El ICANN y sus últimas decisiones -- El DVD gana terreno al VHS -- Costa Rica quiere ser el quinto país en conexiones de banda ancha -- Usuarios del celular quieren nuevos aparatos y más funciones -- ¿Internet estimula la timidez? …”

“…China and India are the only two countries that constitute four realities that are strategically crucial for the global enterprise:* Both provide mega-markets for almost every product and service* Both have platforms that will dram…”

Tabla de Contenidos: “…Introduction -- Design of efficient, dependable SoCs based on cross-layer-reliability approach with emphasis on wireless communication as application and DRAM memories -- CRAU: Compositional System-Level Reliability Analysis in the Presence of Uncertainties -- Semantics-aware Soft Error Handling for Embedded Systems using Compiler-OS Interaction -- ARES: Self-Adaptive Coarse-Grained Reconfigurable Architectures as Reliability Enhancers in Embedded Systems -- Cross-Layer Techniques for Dependable Software Execution on Embedded Systems -- Ambrosia: Cross-layer Modeling and Mitigation of Aging Effects in Embedded Systems -- Cross-Layer Dependability for Embedded Hardware/Software Systems -- Fault-Tolerant Computing with Heterogeneous Hardware/Software Hardening Modes -- Robust Computing for Machine Learning-Based Systems -- Hardening embedded system software -- LIFT: Lifting Device-Level Characteristics for Error Resilient System Level Design: A Crosslayer Approach -- VirTherm-3D: Communication Virtualization Enabling System Management for Dependable 3D MPSoCs -- OTERA: Online Test Strategies for Reliable Reconfigurable Architectures -- Variability-Aware Software: Recent Results and Contributions -- EM Lifetime Constrained Optimization for Multi-Segment Power Grid Networks -- Lightweight Software-Assisted Memory Error Correction -- Reliability-Driven Resource Management for Multi-Core Systems-on-Chip -- Monitor Circuits for Device-Circuit Interaction -- PERCIES: Providing Efficient Reliability in Critical Embedded Systems…”

Tabla de Contenidos: “…Memory systems; Memory technologies; SRAM; EPROM and OTP; Memory organisation; Parity; Error detecting and correcting memory; Access times; Packages; DRAM interfaces; DRAM refresh techniques; Optimizing line length and cache size; Logical vs physical caches; Unified versus Harvard caches; Cache coherency; Case 1: write-through; Case 2: write-back; Case 3: no caching of write cycles; Case 4: write buffer; Bus snooping; The MESI protocol; The MEI protocol; Big and little endian…”

“…Este hecho serÆ el desencadenante de una dramÆtica revelaciðn…”
Trailer en espaæol

Tabla de Contenidos: “…CPU Design Building BlocksDigital Synchronous Logic and Clocks; SRAM and eDRAM; I/O; Intel Server Processors; Introduction to Power; CPU Power Breakdown; Logic Power; I/O Power; Frequency, Voltage, and Temperature Interactions; Power-Saving Techniques; Turn It Off; Turn It Down; Power-Saving Strategies; Race to Idle vs. …”

Tabla de Contenidos: “…Introduction ; 2. Memory - DRAM ; 3. Memory - NAND ; 4. …”

Tabla de Contenidos: “…Franzon 7.1 Introduction 141 7.2 EDA Flows for 3D-IC 141 7.3 Commercial EDA Support 143 7.4 Modular Partitioning Approaches 143 7.5 Circuit Partitioning 145 7.6 Conclusions 146 References 147 8 3D Stacked DRAM Memories 149; Christian Weis, Matthias Jung, and Norbert Wehn 8.1 3D-DRAM Design Space and DRAM Technology Background 150 8.2 Design Space Exploration of 3D-DRAMs 160 8.3 Architectural 3D Stacked DRAM Controller Optimizations 176 8.4 Conclusion 183 References 184 Part II Test 187 9 Cost Modeling for 2.5D and 3D Stacked ICs 189; Mottaqiallah Taouil, Said Hamdioui…”

Tabla de Contenidos: “…Tech Utilities -- Right-Click -- Control Panel -- Device Manager -- System Tools -- Command Line -- Microsoft Management Console -- Administrative Tools -- Action Center (Unique to Windows 7) -- Beyond A+ -- Windows 8 -- Windows Embedded -- Chapter Review -- Questions -- Answers -- Chapter 5 Visible Networks -- Historical/Conceptual -- Networking Technologies -- Topology -- 801 -- Frames and NICs -- Introducing Ethernet -- Network Protocols, LANs, and WANs -- A Short History of the War of the Network Protocols and Why TCP/IP Won -- LANs, Routing, and WANs -- 802 -- Network Organization -- Workgroups -- Domains -- Homegroups -- Chapter Review -- Questions -- Answers -- Chapter 6 Microprocessors -- Historical/Conceptual -- CPU Core Components -- The Man in the Box -- Clock -- Back to the External Data Bus -- Memory -- Memory and RAM -- Address Bus -- 801 -- Modern CPUs -- Manufacturers -- Technology -- Selecting, Installing, and Troubleshooting CPUs -- Selecting a CPU -- Installation Issues -- 802 -- Troubleshooting CPUs -- Beyond A+ -- Intel Atom -- Chapter Review -- Questions -- Answers -- Chapter 7 RAM -- Historical/Conceptual -- Understanding DRAM -- Organizing DRAM -- Practical DRAM -- DRAM Sticks -- Consumer RAM -- 801 -- Types of RAM -- SDRAM -- RDRAM -- DDR SDRAM -- DDR2 -- DDR3 -- RAM Variations -- Working with RAM -- Do You Need More RAM? …”

“…You will understand how persistent memory brings together several new software/hardware requirements, and offers great promise for better performance and faster application startup times—a huge leap forward in byte-addressable capacity compared with current DRAM offerings. This revolutionary new technology gives applications significant performance and capacity improvements over existing technologies. …”