Tabla de Contenidos: “…Locks and Waits AnalysisDissassembly Source View; Parallel Inspector XE; Predefined Analysis Types; Errors and Warnings; Static Security Analysis; Different Approaches to Using Parallel Studio XE; Summary; Chapter 3: Parallel Studio XE for the Impatient; The Four-Step Methodology; Example 1: Working with Cilk Plus; Obtaining a Suitable Serial Program; Running the Serial Example Program; Creating the Project; Running the Serial Version of the Code; Step 1: Analyze the Serial Program; Using Intel Parallel Amplifier XE for Hotspot Analysis; Step 2: Implement Parallelism using Cilk Plus…”

Tabla de Contenidos: “…1.5.5 Portability of Functionality1.5.6 Performance Portability; 1.5.7 Safety, Determinism, and Maintainability; 1.5.8 Overview of Programming Models Used; Cilk Plus; Threading Building Blocks (TBB); OpenMP; Array Building Blocks (ArBB); OpenCL; 1.5.9 When to Use Which Model?…”

Tabla de Contenidos: “…3.9 MULTICORE SYSTEMS3.10 SM; 3.11 COMMUNICATION BETWEEN PARALLEL PROCESSORS; 3.12 SUMMARY OF PARALLEL ARCHITECTURES; Chapter 4: Shared-Memory Multiprocessors; 4.1 INTRODUCTION; 4.2 CACHE COHERENCE AND MEMORY CONSISTENCY; 4.3 SYNCHRONIZATION AND MUTUAL EXCLUSION; Chapter 5: Interconnection Networks; 5.1 INTRODUCTION; 5.2 CLASSIFICATION OF INTERCONNECTION NETWORKS BY LOGICAL TOPOLOGIES; 5.3 INTERCONNECTION NETWORK SWITCH ARCHITECTURE; Chapter 6: Concurrency Platforms; 6.1 INTRODUCTION; 6.2 CONCURRENCY PLATFORMS; 6.3 CILK++; 6.4 OpenMP; 6.5 COMPUTE UNIFIED DEVICE ARCHITECTURE (CUDA)…”

Tabla de Contenidos: “…Front Cover -- Half Title page -- RIVER PUBLISHERS SERIES IN INFORMATIONSCIENCE AND TECHNOLOGY -- Title page -- Copyright page -- Contents -- Preface -- List of Contributors -- List of Figures -- List of Tables -- List of Abbreviations -- Chapter 1 - Introduction -- 1.1 Introduction -- 1.1.1 The Convergence of High-performance and Embedded Computing Domains -- 1.1.2 Parallelization Challenge -- 1.2 The P-SOCRATES Project -- 1.3 Challenges Addressed in This Book -- 1.3.1 Compiler Analysis of Parallel Programs -- 1.3.2 Predictable Scheduling of Parallel Tasks on Many-core Systems -- 1.3.3 Methodology for Measurement-based Timing Analysis -- 1.3.4 Optimized OpenMP Tasking Runtime System -- 1.3.5 Real-time Operating Systems -- 1.4 The UpScale SDK -- 1.5 Summary -- References -- Chapter 2 - Manycore Platforms -- 2.1 Introduction -- 2.2 Manycore Architectures -- 2.2.1 Xeon Phi -- 2.2.2 Pezy SC -- 2.2.3 NVIDIA Tegra X1 -- 2.2.4 Tilera Tile -- 2.2.5 STMicroelectronics STHORM -- 2.2.6 Epiphany-V -- 2.2.7 TI Keystone II -- 2.2.8 Kalray MPPA-256 -- 2.2.8.1 The I/O subsystem -- 2.2.8.2 The Network-on-Chip (NoC) -- 2.2.8.3 The Host-to-IOS communication protocol -- 2.2.8.4 Internal architecture of the compute clusters -- 2.2.8.5 The shared memory -- 2.3 Summary -- References -- Chapter 3 - Predictable Parallel Programming with OpenMP -- 3.1 Introduction -- 3.1.1 Introduction to Parallel Programming Models -- 3.1.1.1 POSIX threads -- 3.1.1.2 OpenCLTM -- 3.1.1.3 NVIDIA R CUDA -- 3.1.1.4 Intel R CilkTM Plus -- 3.1.1.5 Intel R TBB -- 3.1.1.6 OpenMP -- 3.2 The OpenMP Parallel Programming Model -- 3.2.1 Introduction and Evolution of OpenMP -- 3.2.2 Parallel Model of OpenMP -- 3.2.2.1 Execution model -- 3.2.2.2 Acceleration model -- 3.2.2.3 Memory model -- 3.2.3 An OpenMP Example -- 3.3 Timing Properties of the OpenMP Tasking Model…”