Tabla de Contenidos: “…Planning and monitoring tools -- 4.1 Disk Magic -- 4.1.1 Overview and characteristics -- 4.1.2 Output information -- 4.1.3 Disk Magic modeling -- 4.1.4 Disk Magic for zSeries -- 4.1.5 Disk Magic for open systems -- 4.1.6 Workload growth projection -- 4.1.7 Input data needed for DIsk Magic study -- 4.2 Capacity Magic -- 4.2.1 Overview and features -- 4.2.2 Wizard -- 4.2.3 Graphical interface -- 4.2.4 Reports -- 4.2.5 Examples -- 4.3 IBM TotalStorage Productivity Center for Disk -- 4.3.1 IBM TotalStorage Productivity Center -- 4.3.2 IBM TotalStorage Productivity Center for Disk -- 4.3.3 Operation characteristics -- 4.3.4 Using IBM TotalStorage Productivity Center for Disk -- 4.3.5 Exploiting gauges -- 4.3.6 Interpreting the DS6000 performance -- 4.3.7 Performance gauge - considerations -- 4.3.8 IBM TotalStorage Productivity Center for Disk and other tools -- 4.3.9 IBM TotalStorage Productivity Center for Disk in mixed environment -- 4.4 SAN statistics -- 4.5 Monitoring performance through a SAN switch or director -- Chapter 5. …”

Tabla de Contenidos: “…Requirements analysis -- 4.1 Overview -- 4.1.1 Definition of key terms -- 4.1.2 How to gather requirements -- 4.2 High-level business description -- 4.3 Business goals -- 4.4 Assumptions -- 4.5 Existing environment -- 4.5.1 Business perspective -- 4.5.2 IT perspective -- 4.6 Functional requirements -- 4.6.1 Catalog subsystem -- 4.6.2 Member subsystem -- 4.6.3 Order subsystem -- 4.6.4 Marketing subsystem -- 4.7 Non-functional requirements -- 4.7.1 Capacity and performance -- 4.7.2 Availability -- 4.7.3 Security -- 4.7.4 Systems management -- 4.7.5 Scalability -- 4.7.6 Maintainability -- 4.7.7 Manageability -- 4.7.8 System usability -- 4.7.9 Data integrity and failure recovery -- 4.8 Standards and policies -- 4.8.1 Business standards…”

Tabla de Contenidos: “…3.2.5 VST3 and the GUID -- 3.2.6 VST3 Plugin Class Factory -- 3.3 Description: Plugin Description Strings -- 3.4 Description: Plugin Options/Features -- 3.4.1 Side Chain Input -- 3.4.2 Latency -- 3.4.3 Tail Time -- 3.4.4 Custom GUI -- 3.4.5 Factory Presets and State Save/Load -- 3.4.6 VST3 Support for 64-bit Audio -- 3.5 Initialization: Defining Plugin Parameters -- 3.5.1 Thread-Safe Parameter Access -- 3.5.2 Initialization: Defining Plugin Channel I/O Support -- 3.5.3 Initialization: Channel Counts and Sample Rate Information -- 3.6 The Buffer Process Cycle -- 3.6.1 Processing: Updating Plugin Parameters From GUI Controls -- 3.6.2 Processing: Resetting the Algorithm and Preparing for Streaming -- 3.6.3 Processing: Accessing the Audio Buffers -- 3.6.4 Processing: Writing Output Parameters -- 3.6.5 Processing: VST3 Soft Bypass -- 3.7 Destruction/Termination -- 3.8 Retrieving VST3 Host Information -- 3.9 Validating Your Plugin -- 3.10 Using ASPiK to Create VST3 Plugins -- 3.11 Bibliography -- Chapter 4: AU Programming Guide -- 4.1 Setting Up the AU SDK -- 4.1.1 AU Sample Projects -- 4.1.2 AU Documentation -- 4.2 AU Architecture and Anatomy -- 4.2.1 AU Base Classes -- 4.2.2 MacOS Bundle ID -- 4.2.3 AU Programming Notes -- 4.3 Description: Plugin Description Strings -- 4.4 Description: Plugin Options/Features -- 4.4.1 Side Chain Input -- 4.4.2 Latency -- 4.4.3 Tail Time -- 4.4.4 Custom GUI -- 4.4.5 Factory Presets and State Save/Load -- 4.5 Initialization: Defining Plugin Parameters -- 4.5.1 Thread-Safe Parameter Access -- 4.5.2 Initialization: Defining Plugin Channel I/O Support -- 4.5.3 Initialization: Channel Counts and Sample Rate Information -- 4.6 The Buffer Process Cycle -- 4.6.1 Processing: Updating Plugin Parameters From GUI Controls -- 4.6.2 Processing: Resetting the Algorithm and Preparing for Streaming…”

Tabla de Contenidos: “…Auflage -- Kapitel 2: Vorbereitung auf CompTIA A+ -- 2.1 Prüfen Sie Ihr Wissen -- 2.2 Fragen zu einem Computersystem -- 2.2.1 Die Front eines PC-Systems -- 2.2.2 Rückseitige Anschlüsse -- 2.2.3 Blick auf das Mainboard -- Teil I: Alles Blech oder was -- Kapitel 3: Vom Bit bis zum Personal Computer -- 3.1 Die Welt der Elektronik -- 3.2 Ganz klein und ganz groß -- 3.3 Der Personal Computer -- 3.4 Vom Laptop bis zum Smartphone -- 3.5 Smart sind die Geräte -- 3.5.1 Unterhaltung -- 3.5.2 Wearable Computer -- 3.6 Fragen zu diesem Kapitel -- Kapitel 4: Einblick in die Systemarchitektur -- 4.1 Die Systemzentrale: Der Prozessor -- 4.1.1 Single Core, Dual Core, noch mehr Core -- 4.1.2 Intel Core i und AMD Zen -- 4.1.3 Sockel für Prozessoren -- 4.1.4 Die technische Funktion der CPU -- 4.1.5 Der Cache -- 4.2 Mainboard-Komponenten -- 4.2.1 Das Chipset -- 4.2.2 Der DMA-Controller -- 4.2.3 Der Interrupt-Controller -- 4.2.4 Der Taktgeber -- 4.2.5 Mainboard-Formfaktoren -- 4.3 Der Arbeitsspeicher -- 4.3.1 Aufbau von RAM-Bausteinen -- 4.3.2 Aktuelle RAM-Typen hören auf den Namen DDR -- 4.3.3 Single Channel, Dual Channel, Quad Channel -- 4.3.4 Bauformen -- 4.3.5 Was folgt nach DDR4? -- 4.4 BIOS und EFI leben im ROM -- 4.4.1 Das BIOS -- 4.4.2 UEFI folgt auf BIOS -- 4.5 Fragen zu diesem Kapitel -- Kapitel 5: Von Systembussen und Bussystemen -- 5.1 Der Prozessor wartet auf den Bus -- 5.2 Blick auf einen Vorläufer: die PCI-Architektur -- 5.3 PCI-X -- 5.4 PCI-Express -- 5.4.1 PCI-Express-Grafik-Interface -- 5.4.2 Die Weiterentwicklung bei Intel -- 5.4.3 Mini-PCI-Express -- 5.4.4 ExpressCard…”

Tabla de Contenidos: “…The development process -- 4.1 Development process basics -- 4.1.1 Definition of a development process -- 4.1.2 Importance of a development process -- 4.1.3 Realization of a development process -- 4.1.4 Development process principles -- 4.2 Starting a project -- 4.2.1 Understanding your business today -- 4.2.2 Where do you want to go -- 4.2.3 An initial roadmap of how to get there -- 4.3 Understanding and planning a project -- 4.4 Building a solution -- 4.5 Project hand-over -- 4.6 RealEstate application architecture -- 4.6.1 Component-based architecture -- 4.6.2 Layered design -- 4.6.3 Package structure -- 4.6.4 Naming conventions -- Part 2 The sample solution -- Chapter 5. …”

Tabla de Contenidos: “…3.9.1 Predefined Interrupts (0 to 4) -- 3.9.2 User-Defined Software Interrupts -- 3.9.3 User-Defined Hardware (Maskable Interrupts, Type Codes 3210 - 25510) -- 3.10 8086 DMA -- Questions and Problems -- Chapter 4: Intel 80186/80286/80386 -- 4.1 Intel 80186 and 80286 -- 4.1.1 Intel 80186 -- 4.1.2 Intel 80286 -- 4.1.2.a 80286 Memory Management -- 4.1.2.b Protection -- 4.12.c 80286 Exceptions -- 4.2 Intel 80386 -- 4.2.1 Basic 80386 Programming Model -- 4.2.1.a Memory Organization and Segmentation -- 4.2.1.b Data Types -- 4.2.1.c 80386 Registers -- 4.2.1.d 80386 Addressing Modes -- 4.2.2 80386 Instruction Set -- 4.2.2.a Arithmetic Instructions -- 4.2.2.b Bit Manipulation Instructions -- 4.2.2.c Byte-Set-On Condition Instructions -- 4.2.2.d Conditional Jumps and Loops -- 4.2.2.e Data Transfer -- 4.2.2.f Flag Control -- 4.2.2.g Logical -- 4.2.2.h String -- 4.2.2.i Table Look-Up Translation Instruction -- 4.2.2.j High-Level Language Instructions -- 4.2.3 Memory Organization -- 4.2.4 I/O Space -- 4.2.5 80386 Interrupts -- 4.2.6 80386 Reset and Initialization -- 4.2.7 Testability -- 4.2.8 Debugging -- 4.2.9 80386 Pins and Signals -- 4.2.10 80386 Bus Transfer Technique -- 4.2.11 80386 Read and Write Cycles -- 4.2.12 80386 Modes -- 4.2.12.a 80386 Real Mode -- 4.2.12.b Protected Mode -- 4.2.1.2.c Virtual 8086 Mode -- 4.3 80386 System Design -- 4.3.1 80386 Memory Interface -- 4.3.2 80386 I/O -- 4.4 Coprocessor Interface -- 4.4.1 Coprocessor Hardware Concepts -- 4.4.2 Coprocessor Registers -- 4.4.3 80387 Instructions -- Questions and Problems -- Chapter 5: Motorola MC68000 -- 5.1 Introduction -- 5.2 68000 Programming Model -- 5.3 68000 Addressing Structure -- 5.4 68000 Addressing Modes -- 5.4.1 Register Direct Addressing -- 5.4.2 Address Register Indirect Addressing -- 5.4.3 Absolute Addressing -- 5.4.4 Program Counter Relative Addressing…”

Tabla de Contenidos: “…3.3 Resolutions in SAR -- 3.4 SAR Image Formation -- 3.5 Range Compression -- 3.5.1 Matched Filter -- 3.5.1.1 Computing Matched Filter Output via Fourier Processing -- 3.5.1.2 Example for Matched Filtering -- 3.5.2 Ambiguity Function -- 3.5.2.1 Relation to Matched Filter -- 3.5.2.2 Ideal Ambiguity Function -- 3.5.2.3 Rectangular-Pulse Ambiguity Function -- 3.5.2.4 LFM-Pulse Ambiguity Function -- 3.5.3 Pulse Compression -- 3.5.3.1 Detailed Processing of Pulse Compression -- 3.5.3.2 Bandwidth, Resolution, and Compression Issues for LFM Signal -- 3.5.3.3 Pulse Compression Example -- 3.6 Azimuth Compression -- 3.6.1 Processing in Azimuth -- 3.6.2 Azimuth Resolution -- 3.6.3 Relation to ISAR -- 3.7 SAR Imaging -- 3.8 SAR Focusing Algorithms -- 3.8.1 RDA -- 3.8.1.1 Range Compression in RDA -- 3.8.1.2 Azimuth Fourier Transform -- 3.8.1.3 Range Cell Migration Correction -- 3.8.1.4 Azimuth Compression -- 3.8.1.5 Simulated SAR Imaging Example -- 3.8.1.6 Drawbacks of RDA -- 3.8.2 Chirp Scaling Algorithm -- 3.8.3 The ω-kA -- 3.8.4 Back-Projection Algorithm -- 3.9 Example of a Real SAR Imagery -- 3.10 Problems in SAR Imaging -- 3.10.1 Range Migration and Range Walk -- 3.10.2 Motion Errors -- 3.10.3 Speckle Noise -- 3.11 Advanced Topics in SAR -- 3.11.1 SAR Interferometry -- 3.11.2 SAR Polarimetry -- 3.12 Matlab Codes -- References -- Chapter 4 Inverse Synthetic Aperture Radar Imaging and Its Basic Concepts -- 4.1 SAR versus ISAR -- 4.2 The Relation of Scattered Field to the Image Function in ISAR -- 4.3 One-Dimensional (1D) Range Profile -- 4.4 1D Cross-Range Profile -- 4.5 Two-Dimensional (2D) ISAR Image Formation (Small Bandwidth, Small Angle) -- 4.5.1 Resolutions in ISAR -- 4.5.1.1 Range Resolution -- 4.5.1.2 Cross-Range Resolution: -- 4.5.2 Range and Cross-Range Extends -- 4.5.3 Imaging Multibounces in ISAR -- 4.5.4 Sample Design Procedure for ISAR…”

Tabla de Contenidos: “…Auflage -- Kapitel 2: Vorbereitung auf CompTIA A+ -- 2.1 Prüfen Sie Ihr Wissen -- 2.2 Fragen zu einem Computersystem -- 2.2.1 Die Front eines PC-Systems -- 2.2.2 Rückseitige Anschlüsse -- 2.2.3 Blick auf das Mainboard -- Teil I: Alles Blech oder was -- Kapitel 3: Vom Bit bis zum Personal Computer -- 3.1 Die Welt der Elektronik -- 3.1.1 Darstellung von Zahlen -- 3.1.2 Darstellung von Texten -- 3.1.3 Darstellung von Bildern -- 3.1.4 Darstellung von Tönen -- 3.2 Ganz klein und ganz groß -- 3.3 Der Personal Computer -- 3.4 Vom Laptop bis zum Smartphone -- 3.5 Smart sind die Geräte -- 3.5.1 Unterhaltung -- 3.5.2 Wearable Computer -- 3.6 Fragen zu diesem Kapitel -- Kapitel 4: Einblick in die Systemarchitektur -- 4.1 Die Systemzentrale: Der Prozessor -- 4.1.1 Single Core, Dual Core, noch mehr Core -- 4.1.2 Intel Core i und AMD Zen -- 4.1.3 Sockel für Prozessoren -- 4.1.4 Die technische Funktion der CPU -- 4.1.5 Der Cache -- 4.2 Mainboard-Komponenten -- 4.2.1 Das Chipset -- 4.2.2 Der DMA-Controller‌ -- 4.2.3 Der Interrupt-Controller‌ -- 4.2.4 Der Taktgeber‌ -- 4.2.5 Mainboard-Formfaktoren -- 4.3 Der Arbeitsspeicher -- 4.3.1 Aufbau von RAM-Bausteinen -- 4.3.2 Aktuelle RAM-Typen hören auf den Namen DDR -- 4.3.3 Single Channel, Dual Channel, Quad Channel -- 4.3.4 Bauformen -- 4.3.5 Was folgt nach DDR5? -- 4.4 BIOS und EFI leben im ROM -- 4.4.1 Das BIOS -- 4.4.2 UEFI folgt auf BIOS -- 4.5 Der Prozessor wartet auf den Bus -- 4.5.1 Ein Blick in die Vorgeschichte: Die PCI-Architektur -- 4.6 PCI-Express -- 4.6.1 PCI-Express-Grafik-Interface -- 4.6.2 Die Weiterentwicklung bei Intel -- 4.6.3 Mini-PCI-Express…”

Tabla de Contenidos: “…-- 4.2 The North American Grid -- 4.2.1 Grid Structure -- 4.2.2 ACE and Kirchhoff's Law -- 4.2.3 Anatomy of a Blackout -- 4.3 Threat Analysis -- 4.3.1 Attack Scenario 1: Disruption of Fuel Supply to Power Plants -- 4.3.2 Attack Scenario 2: Destruction of Major Transformers -- 4.3.3 Attack Scenario 3: Disruption of SCADA Communications -- 4.3.4 Attack Scenario 4: Creation of a Cascading Transmission Failure -- 4.4 From Death Rays to Vertical Integration -- 4.4.1 Early Regulation -- 4.4.2 Deregulation and EPACT 1992 -- 4.4.3 Electricity Sector ES-ISAC -- 4.5 Out of Orders 888 and 889 Comes Chaos -- 4.5.1 Economics Versus Physics -- 4.5.2 What Increases SOC? …”

Tabla de Contenidos: “…3.3.1.2 The Short Jump -- 3.3.2 Other Forms of the Unconditional Jump Instruction -- 3.3.2.1 Conditional Jumps -- 3.3.2.2 Far Jump -- 3.3.3 The LOOP Instruction -- 3.4 Arithmetic Instructions -- 3.4.1 Flag Control Instructions -- 3.4.2 Addition Instructions -- 3.4.3 Subtraction -- 3.4.4 Compare Instruction -- 3.4.5 Unsigned Multiplication -- 3.4.6 Unsigned Division -- 3.5 Logical Instructions -- 3.6 Shift and Rotate Instructions -- 3.6.1 Shift -- 3.6.2 Rotate Instructions -- Key Points of this Chapter -- Questions -- Exercises -- Chapter4: Programming Concepts - III -- 4.1 String Instructions -- 4.1.1 The MOVS Instruction -- 4.1.2 The CMPS Instruction -- 4.1.3 The SCAS Instruction -- 4.1.4 The STOS and LODS Instructions -- 4.2 Procedures -- 4.2.1 Writing a Procedure -- 4.2.2 Call and Return Instructions -- 4.2.2.1 Intrasegment or 'Near' Call -- 4.2.2.2 Intersegment or Far Call -- 4.2.3 The RET Instruction -- 4.2.4 The Use of the Stack in Procedure Calls -- 4.2.5 Passing Parameters To and From Procedures -- 4.2.5.1 Passing Parameters Through Registers -- 4.2.5.2 Passing Parameters Through Memory -- 4.2.5.3 Passing Parameters Through the Stack -- 4.3 Macros -- 4.3.1 Writing a Macro -- 4.3.2 Using the 'Local' Directive in Macros -- 4.4 Number Format Conversions -- 4.4.1 Packed BCD to Unpacked BCD Conversion -- 4.4.2 BCD Calculations -- 4.5 ASCII Operations -- 4.5.1 ASCII Addition -- 4.5.2 ASCII Subtraction -- 4.5.3 Multiplication and Division -- 4.6 Conversions for Computations and Display/Entry -- 4.6.1 Converting ASCII Numbers to Binary Form -- 4.6.2 Converting Binary Numbers to ASCII Form -- 4.7 Signed Number Arithmetic -- 4.7.1 Comparison of Signed Numbers -- 4.7.2 Signed Multiplication and Division -- 4.7.3 Arithmetic Shift -- 4.8 Programming Using High Level Language Constructs -- Key Points of this Chapter -- Questions -- Exercises…”

“…El formato del mensaje 4.4. Los elementos de un e-mail 4.5. Medición de los resultados Tema 5. …”
Texto completo en Odilo

“…Y este itinerario de expropiación es persuasivo porque, no en vano, reproduce el modelo de Cristo que también adoptó la condición de esclavo (Flp 2,7; 1 Co 9,19) y nació bajo la ley para rescatar a los que estaban bajo ella(Ga 4,4; 1 Co 9,20)…”

“…Die theoretische Annäherung ebenso wie die einzelnen Fallstudien stellen eine Zugangsform dar, die dem Thema signifikant mehr Tiefenschärfe verleiht.« Britta Voß, Freiburger GeschlechterStudien, 23 (2009) »Interessante Perspektiven hinsichtlich weiterführender Fragen, wie die nach Bedeutung und Erfahrung von Sexualität.« Veronika Springmann, www.querelles-net.de, 10.11.2009 »Der Band bietet insgesamt einen sehr guten Überblick über die derzeitigen Forschungsthemen, insbesondere in seinem medialen Schwerpunkt.« Silke Schneider, FEMINA POLITICA, 2 (2009) Besprochen in: IASL online, 18.09.2009, Michael Löffelsender Ariadne, 5 (2010), Laura Schibbe monitor, 44/2 (2010), Eike Sanders…”

“…. · Review core inter-domain routing concepts, and discover how exterior routing protocols have evolved · Master BGP’s modern operational components · Effectively configure and troubleshoot BGP · Control path attributes and selection to define better routes · Take full advantage of NLRI and routing policies · Provide for load balancing and improved network scalability · Extend BGP to multiprotocol environments via MP-BGP · Deploy, configure, manage, troubleshoot, and scale IP multicast routing · Implement Protocol Independent Multicast (PIM): Dense Mode, Sparse Mode, and Bidirectional · Operate, configure, and troubleshoot NAT in IPv4-IPv4 (NAT44) and IPv6-IPv4 (NAT64) environments · Avoid policy errors and other mistakes that damage network performance This book is part of the CCIE Professional Development series, which offers expert-level instruction on network design, deployment, and support methodologies to help networking professionals manage complex networks and prepare for the CCIE exams. …”

“…While at the University of California at Berkeley, he implemented the 4.2BSD fast filesystem and was the Research Computer Scientist at the Berkeley Computer Systems Research Group (CSRG) overseeing the development and release of 4.3BSD and 4.4BSD. He earned his undergraduate degree in electrical engineering from Cornell University and did his graduate work at the University of California at Berkeley, where he received master's degrees in computer science and business administration and a doctoral degree in computer science. …”

“…This edition has been fully updated to incorporate new features in Objective-C programming introduced with Xcode 4.4 (OS X Mountain Lion) and Xcode 4.5 (iOS 6.) …”

“…Las principales barreras para la cirugía de la catarata fueron: el desconocimiento de la enfermedad en 4.4% de los casos, 17.9% esperaba por su maduración y 11.5% presentaba una enfermedad que contraindicaba la cirugía. …”
Enlace del recurso

“…Elementos de una reunión 4.3. Tipos de reuniones 4.4. Fases de una reunión Tema 5. Técnicas de negociación 5.1. …”
Texto completo en Odilo

“…Estrategias de proceso 4.3. Producción ajustada 4.4. Capacidad 4.5. Análisis de equilibrio 4.6. …”
Texto completo en Odilo

“…Superación de filtros 4.4. Los teléfonos móviles Tema 5. La televenta a través del teléfono 5.1. …”
Texto completo en Odilo