Emerging nanoelectronic devices

Detalles Bibliográficos
Otros Autores:	Chen, An (Electronics engineer), editor (editor), Hutchby, James, editor, Zhirnov, Victor V., editor, Bourianoff, George, editor
Formato:	Libro electrónico
Idioma:	Inglés
Publicado:	Chichester, West Sussex, United Kingdom : John Wiley & Sons Inc 2015.
Edición:	1st ed
Materias:	Nanoelectronics. Nanoelectromechanical systems. Nanostructured materials.
Ver en Biblioteca Universitat Ramon Llull:	https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009849101706719

Tabla de Contenidos:

Intro
Title Page
Copyright
Dedication
Preface
List of Contributors
Acronyms
Part One: Introduction
Chapter 1: The Nanoelectronics Roadmap
1.1 Introduction
1.2 Technology Scaling: Impact and Issues
1.3 Technology Scaling: Scaling Limits of Charge-based Devices
1.4 The International Technology Roadmap for Semiconductors
1.5 ITRS Emerging Research Devices International Technology Working Group
1.6 Guiding Performance Criteria
1.7 Selection of Nanodevices as Technology Entries
1.8 Perspectives
References
Chapter 2: What Constitutes a Nanoswitch? A Perspective
2.1 The Search for a Better Switch
2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain
2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain?
2.4 Giant Spin Hall Effect: A Route to Gain
2.5 Other Possibilities for Switches with Gain
2.6 What do Alternative Switches Have to Offer?
2.7 Perspective
2.8 Summary
Acknowledgments
References
Part Two: Nanoelectronic Memories
Chapter 3: Memory Technologies: Status and Perspectives
3.1 Introduction: Baseline Memory Technologies
3.2 Essential Physics of Charge-based Memory
3.3 Dynamic Random Access Memory
3.4 Flash Memory
3.5 Static Random Access Memory
3.6 Summary and Perspective
Appendix: Memory Array Interconnects
Acknowledgments
References
Chapter 4: Spin Transfer Torque Random Access Memory
4.1 Chapter Overview
4.2 Spin Transfer Torque
4.3 STT-RAM Operation
4.4 STT-RAM with Perpendicular Anisotropy
4.5 Stack and Material Engineering for Jc Reduction
4.6 Ultra-Fast Switching of MTJs
4.7 Spin-Orbit Torques for Memory Application
4.8 Current Demonstrations for STT-RAM
4.9 Summary and Perspectives
References
Chapter 5: Phase Change Memory
5.1 Introduction.
5.2 Device Operation
5.3 Material Properties
5.4 Device and Material Scaling to the Nanometer Size
5.5 Multi-Bit Operation and 3D Integration
5.6 Applications
5.7 Future Outlook
5.8 Summary
Acknowledgments
References
Chapter 6: Ferroelectric FET Memory
6.1 Introduction
6.2 Ferroelectric FET for Flash Memory Application
6.3 Ferroelectric FET for SRAM Application
6.4 System Consideration: SSD System with Fe-NAND Flash Memory
6.5 Perspectives and Summary
References
Chapter 7: Nano-Electro-Mechanical (NEM) Memory Devices
7.1 Introduction and Rationale for a Memory Based on NEM Switch
7.2 NEM Relay and Capacitor Memories
7.3 NEM-FET Memory
7.4 Carbon-based NEM Memories
7.5 Opportunities and Challenges for NEM Memories
References
Chapter 8: Redox-based Resistive Memory
8.1 Introduction
8.2 Physical Fundamentals of Redox Memories
8.3 Electrochemical Metallization Memory Cells
8.4 Valence Change Memory Cells
8.5 Performance
8.6 Summary
References
Chapter 9: Electronic Effect Resistive Switching Memories
9.1 Introduction
9.2 Charge Injection and Trapping
9.3 Mott Transition
9.4 Ferroelectric Resistive Switching
9.5 Perspectives
9.6 Summary
References
Chapter 10: Macromolecular Memory
10.1 Chapter Overview
10.2 Macromolecules
10.3 Elementary Physical Chemistry of Macromolecular Memory
10.4 Classes of Macromolecular Memory Materials and Their Performance
10.5 Perspectives
10.6 Summary
Acknowledgments
References
Chapter 11: Molecular Transistors
11.1 Introduction
11.2 Experimental Approaches
11.3 Molecular Transistors
11.4 Molecular Design
11.5 Perspectives
Acknowledgments
References
Chapter 12: Memory Select Devices
12.1 Introduction
12.2 Crossbar Array and Memory Select Devices.
12.3 Memory Select Device Options
12.4 Challenges of Memory Select Devices
12.5 Summary
References
Chapter 13: Emerging Memory Devices: Assessment and Benchmarking
13.1 Introduction
13.2 Common Emerging Memory Terminology and Metrics
13.3 Redox RAM
13.4 Emerging Ferroelectric Memories
13.5 Mott Memory
13.6 Macromolecular Memory
13.7 Carbon-based Resistive Switching Memory
13.8 Molecular Memory
13.9 Assessment and Benchmarking
13.10 Summary and Conclusions
Acknowledgments
References
Part Three: Nanoelectronic Logic and Information Processing
Chapter 14: Re-Invention of FET
14.1 Introduction
14.2 Historical and Future Trend of MOSFETs
14.3 Near-term Solutions
14.4 Long-term Solutions
14.5 Summary
References
Chapter 15: Graphene Electronics
15.1 Introduction
15.2 Properties of Graphene
15.3 Graphene MOSFETs for Mainstream Logic and RF Applications
15.4 Graphene MOSFETs for Nonmainstream Applications
15.5 Graphene NonMOSFET Transistors
15.6 Perspectives
Acknowledgment
References
Chapter 16: Carbon Nanotube Electronics
16.1 Carbon Nanotubes - The Ideal Transistor Channel
16.2 Operation of the CNTFET
16.3 Important Aspects of CNTFETs
16.4 Scaling CNTFETs to the Sub-10 Nanometer Regime
16.5 Material Considerations
16.6 Perspective
16.7 Conclusion
References
Chapter 17: Spintronics
17.1 Introduction
17.2 Spin Transistors
17.3 Magnetic Logic Circuits
17.4 Summary
References
Chapter 18: NEMS Switch Technology
18.1 Electromechanical Switches for Digital Logic
18.2 Actuation Mechanisms
18.3 Electrostatic Switch Designs
18.4 Reliability and Scalability
References
Chapter 19: Atomic Switch
19.1 Chapter Overview
19.2 Historical Background of the Atomic Switch.
19.3 Fundamentals of Atomic Switches
19.4 Various Atomic Switches
19.5 Perspectives
References
Chapter 20: ITRS Assessment and Benchmarking of Emerging Logic Devices
20.1 Introduction
20.2 Overview of the ITRS Roadmap for Emerging Research Logic Devices
20.3 Recent Results for Selected Emerging Devices
20.4 Perspective
20.5 Summary
Acknowledgments
References
Part Four: Concepts for Emerging Architectures
Chapter 21: Nanomagnet Logic: A Magnetic Implementation of Quantum-dot Cellular Automata
21.1 Introduction
21.2 Technology Background
21.3 NML Circuit Design Based on Conventional, Boolean Logic Gates
21.4 Alternative Circuit Design Techniques and Architectures
21.5 Retrospective, Future Challenges, and Future Research Directions
References
Chapter 22: Explorations in Morphic Architectures
22.1 Introduction
22.2 Neuromorphic Architectures
22.3 Cellular Automata Architectures
22.4 Taxonomy of Computational Ability of Architectures
22.5 Summary
References
Chapter 23: Design Considerations for a Computational Architecture of Human Cognition
23.1 Introduction
23.2 Features of Biological Computation
23.3 Evolution of Behavior as a Basis for Cognitive Architecture Design
23.4 Considerations for a Cognitive Architecture
23.5 Emergent Cognition
23.6 Perspectives
References
Chapter 24: Alternative Architectures for NonBoolean Information Processing Systems
24.1 Introduction
24.2 Hierarchical Associative Memory Models
24.3 N-Tree Model
24.4 Summary and Conclusion
Acknowledgments
References
Chapter 25: Storage Class Memory
25.1 Introduction
25.2 Traditional Storage: HDD and Flash Solid-state Drives
25.3 What is Storage Class Memory?
25.4 Target Specifications for SCM
25.5 Device Candidates for SCM.
25.6 Architectural Issues in SCM
25.7 Conclusions
References
Part Five: Summary, Conclusions, and Outlook for Nanoelectronic Devices
Chapter 26: Outlook for Nanoelectronic Devices
26.1 Introduction
26.2 Quantitative Logic Benchmarking for Beyond CMOS Technologies
26.3 Survey-based Critical Assessment of Emerging Devices
26.4 Retrospective Assessment of ERD Tracked Technologies
References
Index
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Emerging nanoelectronic devices

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