Digital Systems Principles and Design (For Anna University)

Digital Systems: Principles and Design (For Anna University) is designed as an ideal textbook for students of electrical engineering. The book's coverage also meets the requirements of the Digital Electronics paper of the Electronics and Communication Engineering course, and of the Digital Prin...

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Detalles Bibliográficos
Autor principal:	Kamal, Raj (-)
Formato:	Libro electrónico
Idioma:	Inglés
Publicado:	Noida : Pearson India 2011.
Colección:	Always learning.
Materias:	Digital electronics. Digital integrated circuits. Electronic digital computers. Computers.
Ver en Biblioteca Universitat Ramon Llull:	https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009820415406719

Tabla de Contenidos:

Cover
Contents
Preface
Acknowledgements
Chapter 1: Basic Digital Concepts
1.1 Concepts of '1's, '0's
1.1.1 Positive Logic
1.1.2 Negative Logic
1.1.3 Popular Representations of the Digital Circuits
1.2 Analog vs. Digital Circuits
Chapter 2: Boolean Algebra and Theorems, Minterms and Maxterms
2.1 The NOT, AND, OR Logic Operations
2.1.1 The NOT Logic Operation
2.1.2 The AND Logic Operation
2.1.3 The OR Logic Operation
2.2 The NAND and NOR Logic Operations
2.2.1 NAND Gate
2.2.2 NOR Gate
2.3 The XOR, NOT-XOR, NOT-NOT Logic Operations
2.3.1 XOR Logic Operation
2.3.2 NOT-XOR (XNOR) Logic Operation
2.3.3 NOT-NOT Logic Operation
2.4 Boolean Algebraic Rules (for Outputs from the Inputs)
2.4.1 OR Rules
2.4.2 AND Rules
2.4.3 NOT Rules (Rules of Complementation)
2.5 Boolean Algebraic Laws
2.5.1 Commutative Laws
2.5.2 Associative Laws
2.5.3 Distributive Laws
2.6 Demorgan Theorems
2.7 The Sum of the Products (SOPs) as per Boolean Expression and Minterms
2.7.1 SOPs for Two Variables (Two Inputs) Case
2.7.2 SOPs for Three Variables (Three Inputs) Case
2.7.3 SOPs for Four Variables (Four Inputs) Case
2.7.4 Conversion of a Boolean Expression or Truth Table Outputs into the Standard SOP Format
2.8 Product of the Sums and Maxterms for a Boolean Expression
2.8.1 POS for Two Variables (Two Inputs) Case
2.8.2 POS for Three Variables (Three Inputs) Case
2.8.3 POS for Four Variables (Four Inputs) Case
2.8.4 Conversion of a Boolean Expression into Standard POS Format
Chapter 3: Karnaugh Map and Minimization Procedures
3.1 The Three-Variable Karnaugh Map and Tables
3.1.1 Karnaugh Map from the Truth Table
3.1.2 Karnaugh Map from the Minterms in a SOP
3.1.3 Karnaugh Map from the Maxterms in a POS
3.2 Four Variable Karnaugh Map and Tables.
3.2.1 Karnaugh Map from the Truth Table
3.2.2 Karnaugh Map from the Minterms in an SOP
3.2.3 Karnaugh Map from the Maxterms in a POS
3.3 Five and Six Variable Karnaugh Maps and Tables
3.4 An Important Feature in the Design of a Karnaugh Map
3.4.1 Only Single Variable Changes into Its Complement in a Pair of Adjacent Cells
3.4.2 Only Two Variables Change into Their Complements in Adjacent Cells in a Square or Column of Four Cells
3.4.3 Three Variables Change into Their Complements in Adjacent Cells in Box of Eight Adjacent Cells
3.4.4 First and Last Columns for First and Last Rows and Purpose of Deciding Adjacency in a Karnaugh Map
3.4.5 Use of Don't Care (or Unspecified) Input Conditions for Purpose of Deciding Adjacencies in a Karnaugh Map
3.5 Simplification of Logic Circuit Relation by Minimization Using Adjacencies
3.5.1 Minimization of a Karnaugh Map Using Pairs of Adjacent Cells
3.5.2 Minimization of a Karnaugh Map Using Quads of Four Adjacent Cells
3.5.3 Minimization of a Karnaugh Map Using Octet of Eight Adjacent Cells
3.5.4 Minimization of a Karnaugh Map Using Offset Adjacencies and Diagonal Adjacencies
3.5.5 Minimization by Finding Prime Implicants
3.6 Drawing of Logic Circuit Using AND-OR Gates, OR-AND Gates, NAND's Only, NOR's Only
3.7 Representations of a Function (Cover) for a Computer-aided Minimization for Simplifying the Logic Circuits
3.7.1 Representation in Cube Format for Computer-aided Minimization
3.7.2 Representation in Four-Dimensional Hypercube Formats for a Computer-aided Minimization
3.7.3 Representation in Hypercube (Multi-dimensional cube) Formats for Computer-aided Minimization
3.8 Multi-Output Simplification
3.8.1 Prime Implicants for Multi-Outputs Case.
3.9 Two Outputs Simplification-Computer-Based Prime Implicants Using Star Product and Sharp Operations
3.9.1 Combination of Two Cubes Differing in One Variable into One Cube-A Star Product Operation
3.9.2 Finding Essential Prime Implicants Using Two Cubes-A Sharp Operation
3.9.3 Computer-Based Minimization Method to Find Minimum Required Cover (SOP function implicants)
3.10 Computer-Based Minimization-Quine-McCluskey Method
3.10.1 Quine-McCluskey Method of Finding Prime Implicants
3.10.2 Finding Minimal Sum from the Prime Implicants for an Output
3.10.3 Finding Minimal Sum for the Multi-Output Case Using Quine-McCluskey Method
Chapter 4: Binary Arithmetic and Decoding and Mux Logic Units
4.1 Binary Arithmetic Units
4.1.1 Binary Addition of Two Bits
4.1.2 Addition of Two Arithmetic Numbers Each of 4 Bits
4.1.3 Subtraction of Two Arithmetic Numbers Each of 4 Bits
4.2 Decoder
4.2.1 Decoder (Line Decoder)
4.2.2 The 1 of 2 and 1 of 4 Line Decoders
4.2.3 The Four-line to 16-line Decoder
4.2.4 Function Specific Decoders
4.3 Encoder
4.3.1 Encoder (Line Encoder)
4.3.2 Encoder (Priority Encoder)
4.3.3 BCD 10 of 1 Four-bit Encoder
4.3.4 Octal 8 of 1 Three-bit Encoder and Hexadecimal Encoder
4.4 Multiplexer
4.4.1 Multiplexer (Line Selector)
4.4.2 Multiplexer with Outputs Enabling Control (gate) Pin(s)
4.5 Demultiplexer
4.5.1 Demultiplexer Definition
Chapter 5: Code Converters, Comparators and Other Logic Processing Circuits
5.1 Code Converters
5.1.1 Codes for Decimal Numbers
5.1.2 Unit Distance Code Converter
5.1.3 ASCII (American Standard Code for Information Interchange) for the Alphanumeric Characters
5.2 Equality and Magnitude Comparators Between Two Four-bit Numbers
5.3 Odd Parity and Even Parity Generators
5.4 The 4-bit AND, OR, XOR Between Two Words.
5.4.1 AND
5.4.2 OR
5.4.3 XOR
5.4.4 Test
Chapter 6: Sequential Logic, Latches and Flip-Flops
6.1 Flip Flop and Latch
6.2 Sr Latch (Set-Reset Latch) Using Cross Coupled NANDs
6.2.1 SR Latch at Various Input Conditions
6.2.2 Difficulties in Using an SR Latch
6.2.3 Timing Diagrams of an SR Latch
6.2.4 Level Clocked SR Latch
6.3 JK Flip-Flop
6.3.1 Explanation of the State Table for the Logic Circuit of an Edge-Triggered JK FF
6.4 T Flip-Flop
6.4.1 T Flip-Flop with Clear and Preset
6.5 D Flip-Flop and Latch
6.5.1 D Flip-Flop
6.5.2 D Flip-Flop with Clear and Preset
6.5.3 D Latch
6.6 Master-Slave RS Flip-Flop
6.7 Master-Slave (Pulse Triggered) JK Flip-Flop
6.7.1 MS JK Flip-Flop with Clear and Preset
6.8 Clock Inputs
6.8.1 Level Clocking of a Clock Input
6.8.2 Edge Triggering at a Clock Input
6.9 Pulse Clocking of the Latches in the Flip-Flops
6.10 Characteristic Equations for the Analysis
Chapter 7: Sequential Circuits Analysis, State Minimization, State Assignment and Circuit Implementation
7.1 General Sequential Circuit with a Memory Section and Combinational Circuits at the Input and Output Stages
7.2 Synchronous and Asynchronous Sequential Circuits
7.2.1 Synchronous Sequential Circuit
7.2.2 Asynchronous Sequential Circuits
7.3 Clocked Sequential Circuit
7.4 Classification of Sequential Circuit as Moore and Mealy State Machine Circuits
7.4.1 Classification of a Sequential Circuit as Moore Model Circuit
7.4.2 Classification of a Sequential Circuit as Mealy Model Circuit
7.5 Analysis Procedure
7.5.1 Excitation Table
7.5.2 Transition Table
7.5.3 State Table
7.5.4 State Diagram
7.6 Conditions of States Equivalency
7.6.1 State Reduction and Minimization Procedure
7.6.2 Assignment of Variables to a State.
7.7 Implementation Procedure
Chapter 8: Sequential Circuits for Registers and Counters
8.1 Registers
8.1.1 Bi-stable Latches as the Register
8.1.2 Parallel-In Parallel-Out Buffer Register
8.1.3 Number of Bits in a Register
8.2 Shift Registers
8.2.1 Serial-In Serial-Out (SISO) Unidirectional Shift Register
8.2.2 Serial-In Parallel-Out (SIPO) Right Shift Register
8.2.3 Parallel-In Serial-Out (PISO) Right Shift Register
8.3 Counter
8.4 Ripple Counter
8.4.1 Cascaded Divide-By-2n Circuit as a Ripple Counter
8.4.2 Modulo-6, Modulo-7 and Modulo-10 Counters
8.4.3 Ring Counter
8.4.4 Johnson Counter (Even Sequences Switch Tail or Twisted Ring Counter)
8.4.5 Odd Sequencer Johnson Counter (Odd Sequencer Switch Tail or Twisted Ring Counter)
8.5 Synchronous Counter
8.5.1 Synchronous Counter Using Additional Logic Circuit
8.6 Asynchronous Clear, Preset and Load (JAM) in a Counter
8.7 Synchronous Clear, Preset and Load Facilities in a Counter
8.8 Timing Diagrams
Chapter 9: Fundamental Mode Sequential Circuits
9.1 General Asynchronous Sequential Circuit
9.2 Unstable Circuit Operation
9.3 Stable Circuit Asynchronous Mode Operation
9.4 Fundamental Mode Asynchronous Circuit
9.4.1 Tabular Representation of Excitation-cum-Transitions of States and Outputs
9.5 Analysis Procedure
9.5.1 Excitation Table
9.5.2 Transition Table
9.5.3 State Table
9.5.4 State Diagram
9.5.5 Flow Table
9.5.6 Example of an Excitation-cum-Transition Table
9.5.7 Flow Table from Excitation-Transition Table
9.5.8 Flow Diagram
9.6 Races
9.6.1 Cycles of the Races
9.7 Race-Free Assignments
Chapter 10: Hazards and Pulse Mode Sequential Circuits
10.1 Hazards
10.1.1 Static-0 Hazard
10.1.2 Static-1 Hazard
10.2 Identifying Static Hazards.
10.2.1 Identification from the Boolean Expressions.

Digital Systems Principles and Design (For Anna University)

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