Engineering digital design
Engineering Digital Design, Second Edition provides the most extensive coverage of any available textbook in digital logic and design. The new REVISED Second Edition published in September of 2002 provides 5 productivity tools free on the accompanying CD ROM. This software is also included on the In...
| Autor principal: | |
|---|---|
| Otros Autores: | |
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
San Diego :
Academic Press
c2000.
|
| Edición: | 2nd ed |
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009755237806719 |
Tabla de Contenidos:
- Cover; Contents; Preface; Chapter 1. Introductory Remarks and Glossary; 1.1 What Is So Special about Digital Systems?; 1.2 The Year 2000 and Beyond?; 1.3 A Word of Warning; 1.4 Glossary of Terms, Expressions, and Abbreviations; Chapter 2. Number Systems, Binary Arithmetic, and Codes; 2.1 Introduction; 2.2 Positional and Polynomial Representations; 2.3 Unsigned Binary Number System; 2.4 Unsigned Binary Coded Decimal, Hexadecimal, and Octal; 2.5 Conversion between Number Systems; 2.6 Signed Binary Numbers; 2.7 Excess (Offset) Representations; 2.8 Floating-Point Number Systems
- 2.9 Binary Arithmetic2.10 Other Codes; Further Reading; Problems; Chapter 3. Background for Digital Design; 3.1 Introduction; 3.2 Binary State Terminology and Mixed Logic Notation; 3.3 Introduction to CMOS Terminology and Symbology; 3.4 Logic Level Conversion: The Inverter; 3.5 Transmission Gates and Tri-State Drivers; 3.6 AND and OR Operators and Their Mixed-Logic Circuit Symbology; 3.7 Logic Level Incompatibility: Complementation; 3.8 Reading and Construction of Mixed-Logic Circuits; 3.9 XOR and EQV Operators and Their Mixed-Logic Circuit Symbology; 3.10 Laws of Boolean Algebra
- 3.11 Laws of XOR Algebra3.12 Worked Examples; Further Reading; Problems; Chapter 4. Logic Function Representation and Minimization; 4.1 Introduction; 4.2 SOP and POS Forms; 4.3 Introduction to Logic Function Graphics; 4.4 Karnaugh Map Function Minimization; 4.5 Multiple Output Optimization; 4.6 Entered Variable K-map Minimization; 4.7 Function Reduction of Five or More Variables; 4.8 Minimization Algorithms and Application; 4.9 Factorization, Resubstitution, and Decomposition Methods; 4.10 Design Area vs Performance; 4.11 Perspective on Logic Minimization and Optimization
- 4.12 Worked EV K-map ExamplesFurther Reading; Problems; Chapter 5. Function Minimization by Using K-map XOR Patterns and Reed-Muller Transformation Forms; 5.1 Introduction; 5.2 XOR-Type Patterns and Extraction of Gate-Minimum Cover from EV K-maps; 5.3 Algebraic Verification of Optimal XOR Function Extraction from K-maps; 5.4 K-map Plotting and Entered Variable XOR Patterns; 5.5 The SOP-to-EXSOP Reed-Muller Transformation; 5.6 The POS-to-EQPOS Reed-Muller Transformation; 5.7 Examples of Minimum Function Extraction; 5.8 Heuristics for CRMT Minimization; 5.9 Incompletely Specified Functions
- 5.10 Multiple Output Functions with Don't Cares5.11 K-map Subfunction Partitioning for Combined CRMT and Two-Level Minimization; 5.12 Perspective on the CRMT and CRMT/Two-Level Minimization Methods; Further Reading; Problems; Chapter 6. Nonarithmetic Combinational Logic Devices; 6.1 Introduction and Background; 6.2 Multiplexers; 6.3 Decoders/Demultiplexers; 6.4 Encoders; 6.5 Code Converters; 6.6 Magnitude Comparators; 6.7 Parity Generators and Error Checking Systems; 6.8 Combinational Shifters; 6.9 Steering Logic and Tri-State Gate Applications
- 6.10 Introduction to VHDL Description of Combinational Primitives
