Network-on-Chip Architecture, Optimization, and Design Explorations
Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (No...
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
London :
IntechOpen
2022.
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| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009746827206719 |
