Proceedings of the 2012 International Symposium on Physical Design
| Autores Corporativos: | , |
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| Otros Autores: | |
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
[Place of publication not identified]
Association for Computing Machinery
2012
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| Colección: | ACM Conferences
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009714121206719 |
Tabla de Contenidos:
- Welcome and keynote address. Lithography till the end of Moore's law / Burn J. Lin
- Advanced processes. Design-aware lithography / Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif. Graph-based subfield scheduling for electron-beam photomask fabrication / Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang. A polynomial time exact algorithm for self-aligned double patterning layout decomposition / Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D.F. Wong. Flexible self-aligned double patterning aware detailed routing with prescribed layout planning / Jhih-Rong Gao, David Z. Pan
- Emerging challenges and technologies. 3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications / Kwang-Ting Tim Cheng, Dmitri B. Strukov. A fast estimation of SRAM failure rate using probability collectives / Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He. Integrated fluidic-chip co-design methodology for digital microfluidic biochips
- Commeroration for Professor C.-L. Liu. Transformation from ad hoc EDA to algorithmic EDA / Jason Cong. On simulated annealing in EDA / Martin D.F. Wong. On pioneering nanometer-era routing problems / Tong Gao, Prashant Saxena. I attended the nineteenth design automation conference / C.L. Liu
- Analog, datapath, and detailed placement. Routability-driven placement algorithm for analog integrated circuits / Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang. Keep it straight: teaching placement how to better handle designs with datapaths . Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles Alpert, Earl E. Swartzlander, Jr., David Z. Pan. Mixed integer programming models for detailed placement / Shuai Li, Cheng-Kok Koh
- Power and thermal modeling and optimization. Power-grid (PG) analysis challenges for large microprocessor designs: (our experience with oracle sparc processor designs) / Alexander Korobkov. Efficient on-line module-level wake-up scheduling for high performance multi-module designs / Ming-Chao Lee, Yiyu Shi, Yu-Guan Chen, Diana Marculescu, Shih-Chieh Chang. Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph / Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng. TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs / Bing Shi, Ankur Srivastava
- Clocking and routing. Construction of minimal functional skew clock trees / Venky Ramachandran. Novel pulsed-latch replacement based on time borrowing and spiral clustering / Chih-Long Chang, Iris H.-R. Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen. On construction low power and robust clock tree via slew budgeting / Yeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen. Optimizing the antenna area and separators in layer assignment of multi-layer global routing / Wen-Hao Liu, Yih-Lang Li
- Gate sizing. Simultaneous clock and data gate sizing algorithm with common global objective / Gregory Shklover, Ben Emanuel. Construction of realistic gate sizing benchmarks with known optimal solutions / Andrew B. Kahng, Seokhyeong Kang. The ISPD-2012 discrete cell sizing contest and benchmark suite / Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven Burns, Gustavo Wilke, Cheng Zhuo
- Congestion-driven logic and physical synthesis. Towards layout-friendly high-level synthesis / Jason Cong, Bin Liu, Guojie Luo, Raghu Prabhakar. Synthesis for advanced nodes : an industry perspective / Janet L. Olson. Reality-driven physical synthesis / Patrick R. Groeneveld
- Floorplanning and mixed-size placement. Optimal slack-driven block shaping algorithm in fixed-outline floorplanning / Jackey Z. Yan, Chris Chu. Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip / Renshen Wang, Nimish Shah. MAPLE : multilevel adaptive placement for mixed-size designs / Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji. A size scaling approach for mixed-size placement / Kalliope Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan
