Scalable shared-memory multiprocessing
Dr. Lenoski and Dr. Weber have experience with leading-edge research and practical issues involved in implementing large-scale parallel systems. They were key contributors to the architecture and design of the DASH multiprocessor. Currently, they are involved with commercializing scalable shared-mem...
| Otros Autores: | , |
|---|---|
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
San Francisco, California :
Morgan Kaufmann Pubhshers, Inc
1995.
|
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009633591506719 |
Tabla de Contenidos:
- Front Cover; Scalable Shared-Memory Multiprocessing; Copyright Page; Foreword; Table of Contents; Preface; PART I: GΕNERAL CONCEPTS; Chapter 1. Multiprocessing and Scalability; 1.1 Multiprocessor Architecture; 1.2 Cache Coherence; 1.3 Scalability; 1.4 Scaling and Processor Grain Size; 1.5 Chapter Conclusions; Chapter 2. Shared-Memory Parallel Programs; 2.1 Basic Concepts; 2.2 Parallel Application Set; 2.3 Simulation Environment; 2.4 Parallel Application Execution Model; 2.5 Parallel Execution under a PRAM Memory Model; 2.6 Parallel Execution with Shared Data Uncached
- 2.7 Parallel Execution with Shared Data Cached2.8 Summary of Results with Diffrent Memory System Models; 2.9 Communication Behavior of Parallel Applications; 2.10 Communication-to-Computation Ratios; 2.11 Invalidation Patterns; 2.12 Chapter Conclusions; Chapter 3. System Performance Issues; 3.1 Memory Latency; 3.2 Memory Latency Reduction; 3.3 Latency Hiding; 3.4 Memory Bandwidth; 3.5 Chapter Conclusions; Chapter 4. System Implementation; 4.1 Scalability of System Costs; 4.2 Implementation Issues and Design Correctness; 4.3 Chapter Conclusions; Chapter 5. Scalable Shared-Memory Systems
- 5.1 Directory-Based Systems5.2 Hierarchical Systems; 5.3 Reflective Memory Systems; 5.4 Non-Cache-Coherent Systems; 5.5 Vector Supercomputer Systems; 5.6 Virtual Shared-Memory Systems; 5.7 Chapter Conclusions; PART II: EXPERIENCE WITH DASH; Chapter 6. DASH Prototype System; 6.1 System Organization; 6.2 Programmer's Model; 6.3 Coherence Protocol; 6.4 Synchronization Protocol; 6.5 Protocol General Exceptions; 6.6 Chapter Conclusions; Chapter 7. Prototype Hardware Structures; 7.1 Base Cluster Hardware; 7.2 Directory Controller; 7.3 Reply Controller; 7.4 Pseudo-CPU
- 7.5 Network and Network Interface7.6 Performance Monitor; 7.7 Logic Overhead of Directory-Based Coherence; 7.8 Chapter Conclusions; Chapter 8. Prototype PerFormance Analysis; 8.1 Base Memory Performance; 8.2 Parallel Application Performance; 8.3 Protocol Effectiveness; 8.4 Chapter Conclusions; PART III: FUTURΕ TRENDS; Chapter 9. TeraDASH; 9.1 TeraDASH System Organization; 9.2 TeraDASH Coherence Protocol; 9.3 TeraDASH Performance; 9.4 Chapter Conclusions; Chapter 10. Conclusions and Future Directions; 10.1 SSMP Design Conclusions; 10.2 Current Trends; 10.3 Future Trends
- APPENDΧ: Multiprocessor SystemsReferences; Index
