Dark silicon and future on-chip systems

Dark silicon and future on-chip systems

Dark Silicon and the Future of On-chip Systems, Volume 110 , the latest release in the Advances in Computers series published since 1960, presents detailed coverage of innovations in computer hardware, software, theory, design and applications, with this release focusing on an Introduction to dark...

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Detalles Bibliográficos
Otros Autores: Hurson, A. R., author (author), Hurson, A. R., editor (editor), Sarbazi-Azad, Hamid, editor
Formato: Libro electrónico
Idioma:Inglés
Publicado: Cambridge, MA : Academic Press, an imprint of Elsevier 2018.
Edición:First edition
Colección:Advances in Computers ; Volume 110
Materias:
Systems on a chip.
Ver en Biblioteca Universitat Ramon Llull:https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009630759506719
Tabla de Contenidos:
  • Front Cover
  • Dark Silicon and Future On-chip Systems
  • Copyright
  • Contents
  • Preface
  • Chapter One: Dark Silicon and the History of Computing
  • 1. Introduction and Background
  • 2. The Single-Core Era
  • 3. The Multicore Era
  • 3.1. Lack of Parallelism
  • 3.2. Off-Chip Bandwidth Constraint
  • 3.3. Power and Energy Constraints
  • 4. The Dark Silicon Era
  • 4.1. Solutions for Parallelism
  • 4.1.1. Last-Level Cache
  • 4.1.2. Coherence Directory
  • 4.1.3. Network-On-Chip
  • 4.2. Solutions for Off-Chip Traffic
  • 4.3. Solutions for Power Consumption
  • 4.3.1. Integration
  • 4.3.2. Specialization
  • 4.3.3. Approximation
  • 5. Conclusion
  • References
  • Chapter Two: Revisiting Processor Allocation and Application Mapping in Future CMPs in Dark Silicon Era
  • 1. Introduction
  • 2. Related Work
  • 3. SCMesh: A Scalable and High Bandwidth NoC
  • 3.1. Power Consumption Analysis
  • 3.2. Managing the Control Signals
  • 4. Strategy 1: Revisiting Processor Allocation
  • 4.1. Policy 1: Reducing Hop Count
  • 4.2. Policy 2: Sharing Resources
  • 4.3. Overhead of Allocation Algorithm
  • 5. Strategy 2: Revisiting Application Mapping
  • 5.1. Top-Level Abstraction of System
  • 5.2. Algorithms for Dark Silicon Aware Mapping
  • 5.2.1. Dark Silicon Aware Algorithm With High Capability of Power Saving
  • 5.2.2. Dark Silicon Aware Algorithm With High Capability of Resource Sharing
  • 5.2.3. Overhead of the Proposed Mapping Algorithms
  • 5.2.3.1. Time Complexity
  • 5.2.3.2. Space complexity
  • 6. Evaluation
  • 6.1. Experimental Setup
  • 6.1.1. Performance Analysis
  • 6.1.2. Power Analysis
  • 6.1.3. Thermal Analysis
  • 6.2. Evaluation of the Mapping Algorithm
  • 6.2.1. Power Budget Estimation
  • 6.2.2. Thermal Analysis
  • 6.2.3. Performance Comparison
  • 6.2.4. Power Consumption
  • 6.2.5. Energy Efficiency
  • 7. Conclusions
  • References.
  • Chapter Three: Multiobjectivism in Dark Silicon Age
  • 1. Introduction and Background
  • 1.1. The Perennial Challenge of Power Management
  • 1.2. The Essence of Efficient Application Mapping Schemes
  • 1.3. The Emergence of Novel Perspectives
  • 2. Shift Sprinting: Reliable Temperature-Aware NoC-Based MCSoC Architecture in Dark Silicon Age
  • 2.1. Preliminaries and Motivations
  • 2.1.1. High-Performance Demands
  • 2.1.2. High-Reliability Demands
  • 2.2. SS Architecture
  • 2.2.1. Core Behavior Model
  • 2.2.2. System Topology
  • 2.2.3. Application Migration Scheme
  • 2.2.4. Controlling Mechanism
  • 2.3. Methodology
  • 2.3.1. Power Model
  • 2.3.2. Thermal Model
  • 2.4. Experimental Results
  • 2.4.1. Performance Evaluation
  • 2.4.2. Power Consumption Measurement
  • 2.4.3. Thermal Analysis
  • 2.4.4. Reliability Assessment
  • 2.5. Summary
  • 3. Round Rotary Mapping: Temperature- and Congestion-Aware Application Mapping Approach for Wireless NoC in Dark Silicon Age
  • 3.1. Preliminaries and Motivations
  • 3.1.1. Congestion
  • 3.1.2. Hot Spot
  • 3.2. RRM Algorithm
  • 3.2.1. System Configuration
  • 3.2.2. Application Representation
  • 3.2.3. Mapping Algorithm
  • 3.2.4. Step-by-Step Examples
  • 3.3. Methodology
  • 3.4. Experimental Results
  • 3.4.1. Hop Counts and Energy Saving
  • 3.4.2. Network Latency and Congestion Avoidance
  • 3.4.3. System Utilization
  • 3.4.4. Thermal Analysis
  • 3.5. Summary
  • 4. Conclusion and the Future Outlook
  • References
  • Chapter Four: Dark Silicon Aware Resource Management for Many-Core Systems
  • 1. Introduction
  • 1.1. Case Study 1: Impact of the Locations of Dark Cores and the v/f Levels of Active Cores on Temperature
  • 1.2. Case Study 2: Impact of TLP and ILP on Performance
  • 1.3. Summary of the Technique Presented in this Chapter
  • 2. State-of-the-Art Resource Management Techniques
  • 3. System Model.
  • 3.1. Application Model
  • 3.2. Thermal Model
  • 4. Problem Definition
  • 5. Dark Silicon Aware Resource Management
  • 5.1. TDP-Constrained Optimal Resource Distribution
  • 5.2. Thermal-Aware Application Mapping
  • 5.3. Thermal-Constrained Resource Adaptation
  • 6. Experimental Evaluations
  • 6.1. Setup
  • 6.2. Results
  • 6.2.1. Evaluation of the Presented Mapping Policy (the Second Step of DsRem)
  • 6.2.2. Evaluation of the Presented Resource Adaptation Policy (the Third Step of DsRem)
  • 6.2.3. Comparison Between DsRem and a State-of-the-Art Technique in Throughput Maximization
  • 6.2.4. Comparison Between DsRem and the State-of-the-Art Boosting Technique
  • 6.3. Evaluation of the Temporal Thermal Gradient
  • 7. Dark Silicon Aware Resource Management for Heterogeneous Many-CoreSystems
  • 8. Conclusions
  • Acknowledgments
  • References
  • Chapter Five: Dynamic Power Management for Dark Silicon Multicore Processors*
  • 1. Introduction
  • 2. Dark Silicon Aware Microarchitectural Adaptation for Homogeneous Multicores
  • 2.1. State of the Art
  • 2.2. Thread Progress Equalization
  • 2.2.1. TPEq Design and Implementation
  • 2.2.1.1. TPEq Optimizer
  • 2.2.1.2. TPEq Predictors
  • 2.2.2. Empirical Analysis of TPEq
  • 3. Dynamic Scheduling for Asymmetric Multicores
  • 3.1. Related Work
  • 3.2. Threshold Policies for Asymmetric Multicores
  • 3.2.1. Empirical Evaluation
  • 4. Dynamic DoP and Cluster Migration on Asymmetric Multicores
  • 4.1. Related Work
  • 4.2. DoPpler Shift
  • 5. Empirical Analysis
  • 5.1. Compared to Homogeneous Multicore + No Dark Silicon
  • 5.2. Compared With Heterogeneous Multicore + No Dark Silicon
  • 5.3. Compared With Homogeneous Multicore With DVFS
  • 6. Conclusion
  • References
  • Chapter Six: Topology Specialization for Networks-on-Chip in the Dark Silicon Era
  • 1. Introduction
  • 2. Dark Silicon
  • 2.1. The Dim Silicon Approach.
  • 2.2. The Dark Silicon Approach
  • 2.3. Bandwidth Wall
  • 2.4. Processing in Memory
  • 3. Core Specialization
  • 4. Specialized NoC for Specialized Cores
  • 5. Low-Latency and Power-Efficient NoC Architectures
  • 5.1. Network Hop Count Reduction
  • 5.2. Blocking Latency Reduction
  • 5.3. Per-Hop Latency Reduction
  • 5.4. Low-Latency Power-Efficient Circuit Technologies
  • 6. Architecture Support for Topology Reconfiguration
  • 6.1. RecNoC Architecture
  • 6.2. Dark Silicon-Aware Reconfigurable NoC
  • 6.2.1. Baseline Wormhole-Switched Router
  • 6.2.2. The New Router Design
  • 7. Topology Reconfiguration Procedure
  • 7.1. Topology Reconfiguration Algorithm
  • 7.2. Topology Reconfiguration for CMP Workloads
  • 8. Evaluation
  • 8.1. CMP Workloads
  • 8.2. Multicore SoC Workloads
  • 8.3. Sensitivity to Ratio of Active to Dark Cores
  • 9. Conclusion
  • References
  • Chapter Seven: Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era
  • 1. Introduction
  • 2. Architecture of SRAM-Based FPGAs
  • 2.1. Configurable Logic Block
  • 2.2. Hard-Core Blocks
  • 2.3. Routing Resources
  • 3. Power Wall and Dark Silicon
  • 4. Logic Block Architectures in Dark Silicon Era
  • 4.1. Low-Power FPGA With Conventional Logic Architecture
  • 4.2. Low-Power FPGAs With Novel Logic Architectures
  • 5. Routing Block Architectures in Dark Silicon Era
  • 5.1. Nonpower Gating Routing Architectures
  • 5.2. Power Gating Routing Architectures
  • 6. Discussion and Conclusion
  • References
  • Back Cover.

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