Radio frequency digital to analog converters : implementation in nanoscale CMOS

Radio frequency digital to analog converters implementation in nanoscale CMOS

With the proliferation of wireless networks, there is a need for more compact, low-cost, power efficient transmitters that are capable of supporting the various communication standards, including Bluetooth, WLAN, GSM/EDGE, WCDMA and 4G of 3GPP cellular. This book describes a novel idea of RF digital...

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Detalles Bibliográficos
Otros Autores: Alavi, Morteza, author (author), Mehta, Jaimin, author, Staszewski, Robert Bogdan, author
Formato: Libro electrónico
Idioma:Inglés
Publicado: Boston, MA : Elsevier [2017]
Edición:First edition
Materias:
Digital-to-analog converters.
Radio frequency.
Ver en Biblioteca Universitat Ramon Llull:https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009630439106719
Tabla de Contenidos:
  • Front Cover
  • Radio-Frequency Digital-to-Analog Converters: Implementation in Nanoscale CMOS
  • Copyright
  • Contents
  • Preface
  • Acknowledgment
  • Acronyms
  • Chapter 1: Introduction
  • 1.1 The Conventional RF Radio
  • 1.2 Motivation
  • 1.3 The Book Objectives
  • 1.3.1 System Simulation of WCDMA Baseband Data
  • 1.3.2 Some Important Figures-of-Merit in RF Transmitters
  • 1.4 Analog Versus Digital RF Transmitters
  • 1.5 Analog-Intensive RF Transmitters
  • 1.6 Digitally Intensive RF Transmitters
  • 1.7 New Paradigm of RF Design in Nanometer-Scale CMOS
  • 1.8 All-Digital Polar Transmitter
  • 1.9 All-Digital I/Q Transmitter
  • 1.10 Conclusion
  • 1.11 Book Outline
  • Chapter 2: Digital polar transmitter architecture
  • 2.1 Introduction to Narrowband Polar Transmitters
  • 2.1.1 Motivation
  • 2.1.1.1 Small-signal polar transmitter
  • 2.1.1.2 Motivation for the digitally intensive amplitude path
  • 2.1.2 Contrast With Conventional Analog Approaches
  • 2.2 Overview of the RFDAC-Based Polar Transmitter Architecture
  • 2.2.1 Overview of the DPA
  • 2.2.2 DCO Operating Frequency and CKV Clock
  • 2.3 Details of Phase Modulation
  • 2.4 Design Challenges for the Small-Signal Polar Transmitter
  • 2.4.1 DCO Phase Noise
  • 2.4.2 DCO Pulling and Pushing
  • 2.4.3 VGA/DPA Nonlinearity
  • 2.4.4 Amplitude-Phase Path Delay Mismatch
  • 2.4.5 Amplitude-Phase Path Transfer Function Mismatch
  • 2.4.6 Amplitude Path DC Offset
  • 2.4.7 Amplitude Path Dynamic Range Limitations
  • 2.4.8 Amplitude Path DAC Mismatches
  • 2.4.9 Additional Distortions in the DPA (DAC/Mixer)
  • Chapter 3: Digital baseband of the polar transmitter
  • 3.1 Overview of the TX Digital Baseband
  • 3.1.1 Pulse Shaping Filter
  • 3.1.2 Resampler
  • 3.1.2.1 Need for a resampler
  • 3.1.2.2 Implementation
  • 3.1.3 CORDIC
  • 3.2 Predistortion Module
  • 3.2.1 Overview
  • 3.2.2 Principle of Operation.
  • 3.2.2.1 Adaptive interpolation
  • 3.2.2.2 Dynamic LUT inversion
  • 3.2.3 Analysis of the Quantization Effects
  • 3.3 Predistortion Self-Calibration
  • 3.3.1 Effect of Temperature Variations on Predistortion
  • 3.4 Interpolative Filter
  • 3.5 Polar Bandwidth Expansion
  • Chapter 4: RF front-end (RFDAC) of the polar transmitter
  • 4.1 Overview of the RF Front-End
  • 4.2 Σ∆ Amplitude Modulation
  • 4.2.1 Σ∆ Overview
  • 4.2.2 Digital Design
  • 4.2.3 Transfer Function and Spectrum
  • 4.3 Digital Pre-PA
  • 4.3.1 Overview of DPA Functionality
  • 4.3.2 Analysis of DPA Quantization Noise
  • 4.3.3 DPA Structural Design
  • 4.4 DPA Transistor Mismatches
  • 4.4.1 Amplitude Mismatch
  • 4.4.2 Phase Mismatch
  • 4.5 Key Categories of Mismatches and DEM
  • 4.5.1 Key Categories
  • 4.5.1.1 MSB (4x) transistor mismatch
  • 4.5.1.2 Unit (1x) transistor mismatch
  • 4.5.1.3 Systematic mismatch between 1x and 4x transistors
  • 4.5.2 Simulation-Based Specifications
  • 4.5.3 Dynamic Element Matching
  • 4.5.4 Measurement Results
  • 4.6 Clock Delay Alignment
  • 4.6.1 Explanation of the Problem
  • 4.6.2 Self-Calibration and Compensation Mechanism
  • 4.7 Analysis of Parasitic Coupling
  • 4.7.1 Possible Coupling Paths
  • 4.7.2 A Novel Method of Characterizing Σ∆ Parasitic Coupling Using Idle-Tones
  • 4.7.3 Relationship Between Idle Tones and Σ∆ Parasitic Coupling
  • Chapter 5: Simulation and measurement results of the polar transmitter
  • 5.1 Simulation Results
  • 5.2 Measurement Results
  • 5.2.1 Predistortion
  • 5.2.2 Transmitter Close-In Performance
  • 5.2.3 Transmitter Wideband Noise Performance
  • 5.2.4 Performance Comparison
  • 5.3 Conclusion
  • Chapter 6: Idea of all-digital I/Q modulator
  • 6.1 Concept of Digital I/Q Transmitter
  • 6.2 Orthogonal Summing Operation of RFDAC
  • 6.3 Conclusion
  • Chapter 7: Orthogonal summation: A 2x3-bit all-digital I/Q RFDAC.
  • 7.1 Circuit Building Blocks of Digital I/Q Modulator
  • 7.1.1 Digitally Controlled Oscillator
  • 7.1.2 Divide-By-Two Circuit
  • 7.1.3 25% Duty Cycle generator
  • 7.1.4 Sign Bit Circuit
  • 7.1.5 Implicit Mixer Circuit
  • 7.1.6 2x3-Bit I/Q Switch Array Circuits
  • 7.2 Measurement Results
  • 7.3 Conclusion
  • Chapter 8: Toward high-resolution RFDAC: The system design perspective
  • 8.1 System Design Considerations
  • 8.2 Conclusion
  • Chapter 9: Differential I/Q DPA and power-combining network
  • 9.1 Idealized Power Combiner With Different DRACs
  • 9.2 A Differential I/Q Class-E-Based Power Combiner
  • 9.3 Efficiency of I/Q RFDAC
  • 9.4 Effect of Rise/Fall Time and Duty Cycle
  • 9.5 Efficiency and Noise at Back-Off Levels
  • 9.6 Design an Efficient Balun for Power Combiner
  • 9.7 Conclusion
  • Chapter 10: A wideband 2x13-bit all-digital I/Q RFDAC
  • 10.1 Clock Input Transformer
  • 10.2 High-Speed Rail-to-Rail Differential Dividers
  • 10.3 Complementary Quadrature Sign Bit
  • 10.4 Differential Quadrature 25% Duty Cycle Generator
  • 10.5 Floorplanning of 2x 13-Bit DRAC
  • 10.6 Thermometer Encoders of 3-to-7 and 4-to-15
  • 10.7 DRAC Unit Cell: MSB and LSB
  • 10.8 MSB/LSB Selection Choices
  • 10.9 Digital I/Q Calibration and DPD Techniques
  • 10.9.1 IQ Image and Leakage Suppression
  • 10.9.2 DPD Based on AM-AM and AM-PM Profiles
  • 10.9.3 DPD Based on I/Q Code Mapping
  • 10.9.4 DPD Required Memory and Time
  • 10.9.5 DPD Effectiveness Against the Temperatureand Aging
  • 10.9.6 Verification of DPD I/Q Code Mapping
  • 10.10 Conclusion
  • Chapter 11: Measurement results of the 2x13-bit I/Q RFDAC
  • 11.1 Measurement Setup
  • 11.2 Static Measurement Results
  • 11.3 Dynamic Measurement Results
  • 11.3.1 LO Leakage and IQ Image Suppression of I/Q RFDAC
  • 11.3.2 The RFDAC's Linearity Using AM-AM/AM-PM Profiles.
  • 11.3.3 The RFDAC's Linearity Using Constellation Mapping
  • 11.4 Conclusion
  • Chapter 12: Future of RFDAC
  • 12.1 The Outcome
  • 12.2 Some Suggestions for Future Developments
  • 12.3 Future Trends
  • Appendix A: Appendix for the polar transmitter
  • A.1 EDGE Modulation
  • A.1.1 Symbol Mapping and Rotation
  • A.1.2 Pulse Shaping Filter and Modulation
  • A.2 RF System Specifications for the EDGE Transmitter
  • A.3 Details of the Simulation Model
  • A.3.1 Digital Amplitude and Phase Data Generation
  • A.3.2 RF Front-End Model
  • Appendix B: Appendix for I/Q RFDAC
  • B.1 Universal Asynchronous Receiver/Transmitter
  • B.2 Matching Network Equations
  • B.3 AM-AM/AM-PM Relationship
  • B.4 DPD Bandwidth Expansion
  • References
  • Index
  • Back Cover.

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