Design recipes for FPGAs
Design Recipes for FPGAs provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your ap...
| Otros Autores: | |
|---|---|
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam, Netherlands :
Newnes
2016.
|
| Edición: | Second edition |
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009628812206719 |
Tabla de Contenidos:
- Front Cover
- Design Recipes for FPGAs: Using Verilog and VHDL
- Copyright
- Contents
- Preface to the Second Edition
- Preface to the First Edition
- Acknowledgments
- Part 1: Overview
- Chapter 1: Introduction
- 1.1 Overview
- 1.2 Verilog vs. VHDL
- 1.3 Why FPGAs?
- 1.4 Summary
- Chapter 2: An FPGA Primer
- 2.1 Introduction
- 2.2 FPGA Evolution
- 2.3 Programmable Logic Devices
- 2.4 Field Programmable Gate Arrays
- 2.5 FPGA Design Techniques
- 2.6 Design Constraints using FPGAs
- 2.7 Development Kits and Boards
- 2.8 Summary
- Chapter 3: A VHDL Primer: The Essentials
- 3.1 Introduction
- 3.2 Entity: Model Interface
- 3.2.1 The Entity Definition
- 3.2.2 Ports
- 3.2.3 Generics
- 3.2.4 Constants
- 3.2.5 Entity Examples
- 3.3 Architecture: Model Behavior
- 3.3.1 Basic Definition of An Architecture
- 3.3.2 Architecture Declaration Section
- 3.3.3 Architecture Statement Section
- 3.4 Process: Basic Functional Unit in VHDL
- 3.5 Basic Variable Types and Operators
- 3.5.1 Constants
- 3.5.2 Signals
- 3.5.3 Variables
- 3.5.4 Boolean Operators
- 3.5.5 Arithmetic Operators
- 3.5.6 Comparison Operators
- 3.5.7 Logical Shifting Functions
- 3.5.8 Concatenation
- 3.6 Decisions and Loops
- 3.6.1 If-Then-Else
- 3.6.2 Case
- 3.6.3 For
- 3.6.4 While and Loop
- 3.6.5 Exit
- 3.6.6 Next
- 3.7 Hierarchical Design
- 3.7.1 Functions
- 3.7.2 Packages
- 3.7.3 Components
- 3.7.4 Procedures
- 3.8 Debugging Models
- 3.8.1 Assertions
- 3.9 Basic Data Types
- 3.9.1 Basic Types
- 3.9.2 Data Type: bit
- 3.9.3 Data Type: Boolean
- 3.9.4 Data Type: Integer
- 3.9.5 Integer Subtypes: Natural
- 3.9.6 Integer Subtypes: Positive
- 3.9.7 Data Type: Character
- 3.9.8 Data Type: Real
- 3.9.9 Data Type: Time
- 3.10 Summary
- Chapter 4: A Verilog Primer: The Essentials
- 4.1 Introduction
- 4.2 Modules
- 4.3 Connections.
- 4.4 Wires and Registers
- 4.5 Defining the Module Behavior
- 4.6 Parameters
- 4.7 Variables
- 4.8 Data Types
- 4.9 Decision Making
- 4.10 Loops
- 4.11 Summary
- Chapter 5: Design Automation of FPGAs
- 5.1 Introduction
- 5.2 Simulation
- 5.2.1 Simulators
- 5.2.2 Test Benches
- 5.2.3 Test Bench Goals
- 5.2.4 Simple Test Bench: Instantiating Components
- 5.2.5 Adding Stimuli
- 5.2.6 Assertions
- 5.3 Libraries
- 5.3.1 Introduction
- 5.3.2 Using Libraries
- 5.3.3 Std_logic Libraries
- 5.4 std_logic Type Definition
- 5.5 Synthesis
- 5.5.1 Design Flow for Synthesis
- 5.5.2 Synthesis Issues
- 5.6 RTL Design Flow
- 5.7 Physical Design Flow
- 5.8 Place and Route
- 5.8.1 Recursive Cut
- 5.8.2 Simulated Annealing
- 5.9 Timing Analysis
- 5.10 Design Pitfalls
- 5.10.1 Initialization
- 5.10.2 Floating Point Numbers and Operations
- 5.11 Summary
- Chapter 6: Synthesis
- 6.1 Introduction
- 6.1.1 HDL Supported in RTL Synthesis
- Initial conditions
- Concurrent edges
- 6.2 Numeric Types
- 6.3 Wait Statements
- 6.4 Assertions
- 6.5 Loops
- 6.6 Some Interesting Cases Where Synthesis May Fail
- 6.7 What Is Being Synthesized?
- 6.7.1 Overall Design Structure
- 6.7.2 Controller
- 6.7.3 Data Path
- 6.8 Summary
- Part 2: Introduction to FPGA Applications
- Chapter 7: High Speed Video Application
- 7.1 Introduction
- 7.2 The Camera Link Interface
- 7.2.1 Hardware Interface
- 7.2.2 Data Rates
- 7.2.3 The Bayer Pattern
- 7.2.4 Memory Requirements
- 7.3 Getting Started
- 7.4 Specifying the Interfaces
- 7.5 Defining the Top Level Design
- 7.6 System Block Definitions and Interfaces
- 7.6.1 Overall System Decomposition
- 7.6.2 Mouse and Keyboard Interfaces
- 7.6.3 Memory Interface
- 7.6.4 The Display Interface: VGA
- 7.7 The Camera Link Interface
- 7.8 The PC Interface
- 7.9 Summary.
- Chapter 8: Simple Embedded Processors
- 8.1 Introduction
- 8.2 A Simple Embedded Processor
- 8.2.1 Embedded Processor Architecture
- 8.2.2 Basic Instructions
- 8.2.3 Fetch Execute Cycle
- 8.2.4 Embedded Processor Register Allocation
- 8.2.5 A Basic Instruction Set
- 8.2.6 Structural or Behavioral?
- 8.2.7 Machine Code Instruction Set
- 8.2.8 Structural Elements of the Microprocessor
- 8.3 A Simple Embedded Processor Implemented in VHDL
- 8.3.1 Processor Functions Package
- 8.3.2 The Program Counter
- 8.3.3 The Instruction Register
- 8.3.4 The Arithmetic and Logic Unit
- 8.3.5 The Memory
- 8.3.6 Microcontroller Controller
- 8.3.7 Summary of a Simple Microprocessor Implemented in VHDL
- 8.4 A Simple Embedded Processor Implemented in Verilog
- 8.4.1 The Program Counter
- 8.4.2 The Instruction Register
- 8.4.3 Memory Data Register
- 8.4.4 Memory Address Register
- 8.4.5 The Arithmetic and Logic Unit
- 8.4.6 The Memory
- 8.4.7 Microcontroller Controller
- 8.4.8 Summary of a Simple Verilog Microprocessor
- 8.5 Soft Core Processors on an FPGA
- 8.6 Summary
- Part 3: Designer's Toolbox
- Chapter 9: Digital Filters
- 9.1 Introduction
- 9.2 Converting S Domain to Z Domain
- 9.3 Implementing Z Domain Functions in VHDL
- 9.3.1 Introduction
- 9.3.2 Gain Block
- 9.3.3 Sum and Difference
- 9.3.4 Division Model
- 9.3.5 Unit Delay Model
- 9.4 Basic Low Pass Filter Model
- 9.5 Implementing Z Domain Functions in Verilog
- 9.5.1 Gain Block
- 9.5.2 Sum and Difference
- 9.5.3 Unit Delay Model
- 9.6 Finite Impulse Response Filters
- 9.7 Infinite Impulse Response Filters
- 9.8 Summary
- Chapter 10: Secure Systems
- 10.1 Introduction to Block Ciphers
- 10.2 Feistel Lattice Structures
- 10.3 The Data Encryption Standard (DES)
- 10.3.1 Introduction
- 10.3.2 DES VHDL Implementation
- 10.3.3 DES Verilog Implementation.
- 10.3.4 Validation of DES
- 10.4 Advanced Encryption Standard
- 10.4.1 Implementing AES in VHDL
- 10.5 Summary
- Chapter 11: Memory
- 11.1 Introduction
- 11.2 Modeling Memory in HDLs
- 11.3 Read Only Memory
- 11.4 Random Access Memory
- 11.5 Synchronous RAM
- 11.6 Flash Memory
- 11.7 Summary
- Chapter 12: PS/2 Mouse Interface
- 12.1 Introduction
- 12.2 PS/2 Mouse Basics
- 12.3 PS/2 Mouse Commands
- 12.4 PS/2 Mouse Data Packets
- 12.5 PS/2 Operation Modes
- 12.6 PS/2 Mouse with Wheel
- 12.7 Basic PS/2 Mouse Handler VHDL
- 12.8 Modified PS/2 Mouse Handler VHDL
- 12.9 Basic PS/2 Mouse Handler in Verilog
- 12.10 Summary
- Chapter 13: PS/2 Keyboard Interface
- 13.1 Introduction
- 13.2 PS/2 Keyboard Basics
- 13.3 PS/2 Keyboard Commands
- 13.4 PS/2 Keyboard Data Packets
- 13.5 PS/2 Keyboard Operation Modes
- 13.5.1 Basic PS/2 Keyboard Handler in VHDL
- 13.5.2 Modified PS/2 Keyboard Handler in VHDL
- 13.5.3 Basic PS/2 Keyboard Handler in Verilog
- 13.6 Summary
- Chapter 14: A Simple VGA Interface
- 14.1 Introduction
- 14.2 Basic Pixel Timing
- 14.3 Image Handling
- 14.4 A VGA Interface in VHDL
- 14.4.1 VHDL Top Level Entity for VGA Handling
- 14.4.2 Horizontal Sync
- 14.4.3 Vertical Sync
- 14.4.4 Horizontal and Vertical Blanking Pulses
- 14.4.5 Calculating the Correct Pixel Data
- 14.5 A VGA Interface in Verilog
- 14.5.1 Verilog Top Level Module for VGA Handling
- 14.5.2 Horizontal Sync
- 14.5.3 Vertical Sync
- 14.5.4 Horizontal and Vertical Blanking Pulses
- 14.5.5 Calculating the Correct Pixel Data
- 14.6 Summary
- Chapter 15: Serial Communications
- 15.1 Introduction
- 15.2 Manchester Encoding and Decoding
- 15.3 Implementing the Manchester Encoding Scheme using VHDL
- 15.4 Implementing the Manchester Encoding Scheme using Verilog
- 15.5 NRZ (Non-Return-to-Zero) Coding and Decoding.
- 15.6 NRZI (Non-Return-to-Zero-Inverted) Coding and Decoding
- 15.6.1 NRZI Coding and Decoding in VHDL
- 15.6.2 NRZI Coding and Decoding in Verilog
- 15.7 RS-232
- 15.7.1 Introduction
- 15.7.2 RS-232 Baud Rate Generator
- 15.7.3 RS-232 Receiver
- 15.8 Universal Serial Bus
- 15.9 Summary
- Part 4: Optimizing Designs
- Chapter 16: Design Optimization
- 16.1 Introduction
- 16.2 Techniques for Logic Optimization
- 16.3 Improving Performance
- 16.4 Critical Path Analysis
- 16.5 Summary
- Chapter 17: Behavioral Modeling in using HDLs
- 17.1 Introduction
- 17.2 How to Go from RTL to Behavioral HDL Descriptions
- 17.3 Implementing the Behavioral Model using VHDL
- 17.4 Implementing the Behavioral Model using Verilog
- 17.5 Summary
- Chapter 18: Mixed Signal Modeling
- 18.1 Introduction
- 18.2 Basic Modeling Approach for VHDL-AMS
- 18.3 Introduction to VHDL-AMS
- 18.4 VHDL-AMS Analog Pins: TERMINALS
- 18.5 Mixed Domain Modeling
- 18.6 VHDL-AMS Analog Variables: Quantities
- 18.7 Simultaneous Equations in VHDL-AMS
- 18.8 A VHDL-AMS Example: A DC Voltage Source
- 18.9 A VHDL-AMS Example: Resistor
- 18.10 Differential Equations in VHDL-AMS
- 18.11 Mixed-Signal Modeling with VHDL-AMS
- 18.12 A Basic Switch Model
- 18.13 Basic VHDL-AMS Comparator Model
- 18.14 Multiple Domain Modeling
- 18.15 Introduction to Verilog-AMS
- 18.16 Verilog-AMS: Analog ports
- 18.17 Mixed Domain Modeling in Verilog-AMS
- 18.18 Verilog-AMS Analog Variables
- 18.19 Verilog-AMS Analog Equations
- 18.20 A Verilog-AMS Example
- 18.20.1 DC Voltage Source
- 18.20.2 Resistor
- 18.21 Differential Equations in Verilog-AMS
- 18.22 Mixed Signal Modeling with Verilog-AMS
- 18.23 Multiple Domain Modeling using Verilog-AMS
- 18.24 Summary
- Chapter 19: Design Optimization Example: DES
- 19.1 Introduction
- 19.2 The Data Encryption Standard.
- 19.3 MOODS.
