FPGAs 101 everything you need to know to get started
FPGAs (Field-Programmable Gate Arrays) can be found in applications such as smart phones, mp3 players, medical imaging devices, and for aerospace and defense technology. FPGAs consist of logic blocks and programmable interconnects. This allows an engineer to start with a blank slate and program the...
| Autor principal: | |
|---|---|
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Newnes
c2010.
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| Edición: | 1st edition |
| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627987806719 |
Tabla de Contenidos:
- Front Cover; FPGAs 101; Copyright Page; Contents; About the Author; Acknowledgments; About This Book; Acronyms; Chapter 1: Getting Started; 1.1. Introduction; 1.1.1. VHDL; 1.2. Reserved Words; 1.3. Tips for Writing Good Code; 1.3.1. Tip 1. Use Comments to Convey Information about the Code; 1.3.2. Tip 2. Indent for Clarity and Readability; 1.3.3. Tip 3. Use Standard Format Convention; 1.3.4. Tip 4. Include a Header Section; 1.3.5. Tip 5. Use Brief Descriptive Names; 1.4. HDL Text Editors; 1.4.1. Standalone Text Editor; 1.4.2. Fee-Based Text Editor; 1.5. Editor Features
- 1.5.1. Syntax Color Highlighting1.5.2. Language Templates; 1.5.3. Row and Column Editor; 1.5.4. Comment/Uncomment Selected Text; 1.5.5. Indent/Unindent Selected Text; 1.5.6. Predefined Font Convention; 1.6. Signals; 1.6.1. Signal Data Types; 1.6.2. Signal Names; 1.7. File Structure; 1.7.1. Optional Header Section; 1.7.2. Library Declaration; 1.7.3. Entity Section; 1.7.4. Architecture Section; 1.8. Starter Tips; 1.9. Chapter Overview; Chapter 2: Simple Designs; 2.1. Introduction; 2.2. Starter Template; 2.3. Mathematical Functions; 2.4. Logic Gate; 2.5. D Flip-Flop; 2.6. Latch
- 2.7. Shift Register2.8. Comparator; 2.9. Binary Counter; 2.10. Conversion Functions; 2.11. Read File; 2.12. Write File; 2.13. Chapter Overview; Chapter 3: FPGA Development Phases; 3.1. Introduction; 3.2. What Is a Field Programmable Gate Array?; 3.3. I/O Interfaces; 3.4. Basic Logic Building Blocks; 3.5. Ability to Interconnect; 3.6. Programmable Logic Device Options; 3.7. FPGA Development Phases; 3.8. Chapter Overview; Chapter 4: Design; 4.1. Introduction; 4.2. What Is the Design Phase?; 4.3. Design Package; 4.4. Evaluating the Design Package; 4.4.1. Package Analysis
- 4.4.2. Getting Clarification4.4.3. Organization; 4.5. Predesign Decisions; 4.5.1. Design Format; 4.5.2. FPGA Manufacturer; 4.5.3. Development Tools; 4.6. Creating Design Options; 4.7. Automatic Code Generators; 4.8. Manual Code Generation; 4.8.1. Design Package; 4.9. Chapter Overview; Chapter 5: Simulation; 5.1. Introduction; 5.2. What Is Simulation?; 5.3. Simulation Tools; 5.4. Levels of Simulation; 5.5. Test Cases; 5.6. Stimulus; 5.6.1. Interactive Stimulus; 5.6.2. Graphical Test Bench; 5.6.3. HDL Testbench; 5.6.4. Manual Testbench; 5.6.5. Simulation Phase Outputs
- 5.6.6. Automatic Testbench5.6.7. Capture Data; 5.7. Simulation Tutorial; 5.8. Chapter Overview; Chapter 6: Synthesis; 6.1. Introduction; 6.2. What Is Design Synthesis?; 6.2.1. Design Check and Resource Association; 6.2.2. Optimization; 6.2.3. Technology Mapping; 6.3. Synthesis Phase Tools; 6.3.1. Vendors and Features; 6.3.2. Synthesis Tool Setup; 6.4. Synthesis Input; 6.5. Synthesis Output Files; 6.5.1. Netlists; 6.5.2. Status Reports; 6.5.3. Schematic Views; 6.5.4. Technology Schematic View; 6.6. Synthesis Tutorial; 6.7. Chapter Overview; Chapter 7: Implementation; 7.1. Introduction
- 7.2. What Is Implementation?
