The designer's guide to the Cortex-M processor family a tutorial approach
The Designer's Guide to the Cortex-M Family is a tutorial-based book giving the key concepts required to develop programs in C with a Cortex M-based processor. The book begins with an overview of the Cortex-M family, giving architectural descriptions supported with practical examples, enabling...
| Autor principal: | |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Elsevier/Newnes
2013.
Oxford : 2013. |
| Edición: | 1st edition |
| Colección: | Gale eBooks
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627675606719 |
Tabla de Contenidos:
- Front Cover; The Designer's Guide to the Cortex-M Processor Family; Copyright Page; Contents; Foreword; Preface; Acknowledgments; About the Author; 1 Introduction to the Cortex-M Processor Family; Cortex Profiles; Cortex-M3; Advanced Architectural Features; Cortex-M0; Cortex-M0+; Cortex-M4; DSP Instructions; 2 Developing Software for the Cortex-M Family; Introduction; Keil Microcontroller Development Kit; The Tutorial Exercises; Installation; Exercise Building a First Program; The Blinky Project; Register Window; Disassembly Window; Project Configuration; Hardware Debug
- 3 Cortex-M ArchitectureIntroduction; Cortex-M Instruction Set; Programmer's Model and CPU Registers; Program Status Register; Q Bit and Saturated Math Instructions; Interrupts and Multicycle Instructions; Conditional Execution-IF THEN Blocks; Exercise: Saturated Math and Conditional Execution; Cortex-M Memory Map and Busses; Write Buffer; Memory Barrier Instructions; System Control Block; Bit Manipulation; Exercise: Bit Banding; Dedicated Bit Manipulation Instructions; Systick Timer; Nested Vector Interrupt Controller; Operating Modes; Interrupt Handling-Entry; Interrupt Handling-Exit
- Interrupt Handling-Exit: Important!Exercise: Systick Interrupt; Cortex-M Processor Exceptions; Usage Fault; Bus Fault; Memory Manager Fault; Hard Fault; Enabling Fault Exceptions; Priority and Preemption; Groups and Subgroups; Run Time Priority Control; Exception Model; NVIC Tail Chaining; NVIC Late Arriving; NVIC POP Preemption; Exercise: Working with Multiple Interrupts; Bootloader Support; Exercise: Bootloader; Power Management; Entering Low-Power Modes; Configuring the Low-Power Modes; Exercise: Low-Power Modes; Moving from the Cortex-M3; Cortex-M4; Cortex-M0; Cortex-M0+
- 4 Cortex Microcontroller Software Interface StandardIntroduction; CMSIS Specifications; CMSIS Core; CMSIS RTOS; CMSIS DSP; CMSIS SVD and DAP; Foundations of CMSIS; Coding Rules; MISRA C; CMSIS Core Structure; Startup Code; System Code; Device Header File; CMSIS Core Header Files; Interrupts and Exceptions; Exercise: CMSIS and User Code Comparison; CMSIS Core Register Access; CMSIS Core CPU Intrinsic Instructions; Exercise: Intrinsic Bit Manipulation; CMSIS SIMD Intrinsics; CMSIS Core Debug Functions; Exercise: Simple ITM; 5 Advanced Architecture Features; Introduction
- Cortex Processor Operating ModesExercise: Stack Configuration; Supervisor Call; Exercise: SVC; Pend_SVC Exception; Example: Pend_SVC; Interprocessor Events; Exclusive Access; Exercise: Exclusive Access; Memory Protection Unit; Configuring the MPU; Exercise: MPU Configuration; MPU Subregions; MPU Limitations; AHB Lite Bus Interface; 6 Developing with CMSIS RTOS; Introduction; Getting Started; Setting Up a Project; First Steps with CMSIS RTOS; Threads; Starting the RTOS; Exercise: A First CMSIS RTOS Project; Creating Threads; Exercise: Creating and Managing Threads
- Thread Management and Priority
