Verification techniques for system-level design
This book will explain how to verify SoC (Systems on Chip) logic designs using "formal? and "semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the...
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| Otros Autores: | , |
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers
c2008.
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| Edición: | 1st edition |
| Colección: | Morgan Kaufmann series in systems on silicon.
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| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627619006719 |
