Low-power design of nanometer FPGAs architecture and EDA
Low-Power Design of Nanometer FPGAs Architecture and EDA is an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circu...
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
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San Francisco, CA : Oxford :
Morgan Kaufmann ; Elsevier Science [distributor]
2009.
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| Colección: | Morgan Kaufmann series in systems on silicon.
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| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627537306719 |
Tabla de Contenidos:
- Front Cover; Title Page; Copyright Page; Dedication Page; Table of Contents; Author Bios; Chapter 1. FPGA Overview: Architecture and CAD; 1.1 Introduction; 1.2 FPGA Logic Resources Architecture; 1.2.1 Altera Stratix IV Logic Resources; 1.2.2 Xilinx Virtex-5 Logic Resources; 1.2.3 Actel ProASIC3/IGLOO Logic Resources; 1.2.4 Actel Axcelerator Logic Resources; 1.3 FPGA Routing Resources Architecture; 1.4 CAD for FPGAs; 1.4.1 Logic Synthesis; 1.4.2 Packing; 1.4.3 Placement; 1.4.4 Timing Analysis; 1.4.5 Routing; 1.5 Versatile Place and Route (VPR) CAD Tool; 1.5.1 VPR Architectural Assumptions
- 1.5.2 Basic Logic Packing Algorithm: VPack1.5.3 Timing-Driven Logic Block Packing: T-VPack; 1.5.4 Placement: VPR; 1.5.5 Routing: VPR; Chapter 2. Power Dissipation in Modern FPGAs; 2.1 CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits; 2.2 Dynamic Power in FPGAs; 2.3 Leakage Power in FPGAs; 2.3.1 CMOS Device Leakage Mechanisms; 2.3.2 Current Situation of Leakage Power in Nanometer FPGAs; Chapter 3. Power Estimation in FPGAs; 3.1 Introduction; 3.2 Power Estimation in VLSI: An Overview; 3.2.1 Simulation-Based Power Estimation Techniques
- 3.2.2 Probabilistic-Based Power Estimation Techniques3.3 Commercial FPGA Power Estimation Techniques; 3.3.1 Spreadsheet Power Estimation Tools; 3.3.2 CAD Power Estimation Tools; 3.4 A Survey of FPGA Power Estimation Techniques; 3.4.1 Linear Regression-Based Power Modeling; 3.4.2 Probabilistic FPGA Power Models; 3.4.3 Look-up Table-Based FPGA Power Models; 3.5 A Complete Analytical FPGA Power Model under Spatial Correlation; 3.5.1 Spatial Correlation and Signal Probability Calculations; 3.5.2 Exploration Phase: Locating Spatial Correlation
- 3.5.3 Signal Probabilities Calculation Algorithm under Spatial Correlation3.5.4 Power Calculations Due to Glitches; 3.5.5 Signal Probabilities and Power Dissipation; 3.5.6 Results and Discussion; Chapter 4. Dynamic Power Reduction Techniques in FPGAs; 4.1 Multiple Supply Voltages; 4.1.1 Predefined Dual-VDD Dual-VTH FPGAs; 4.1.2 Programmable Dual-VDD; 4.1.3 Other Dual-VDD FPGA Techniques; 4.2 Reducing Glitches in FPGAs; 4.2.1 Glitch Power Reduction Using Delay Insertion; 4.2.2 Multiphase Flip-Flop Insertion for Glitch Power Reduction in FPGAs
- 4.2.3 Negative Edge Flip-Flop Insertion for Glitch Power Reduction in FPGAs4.2.4 Behavioral Synthesis with Flip-Flop Insertion for Glitch Power Reduction in FPGAs; 4.3 CAD Techniques for Reducing Dynamic Power in FPGAs; 4.3.1 Power Reduction Techniques during Technology Mapping; 4.3.2 Power Reduction Techniques during Clustering; 4.3.3 Power Reduction Techniques during Placement and Routing; Chapter 5. Leakage Power Reduction in FPGAs Using MTCMOS Techniques; 5.1 Introduction; 5.2 MTCMOS FPGA Architecture; 5.3 Sleep Transistor Design and Discharge Current Processing
- 5.3.1 Sleep Transistor Sizing
