Network processors architecture, programming, and implementation
Network processors are the basic building blocks of today's high-speed, high-demand, quality-oriented communication networks. Designing and implementing network processors requires a new programming paradigm and an in-depth understanding of network processing requirements. This book leads the r...
| Autor principal: | |
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| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann
c2008.
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| Edición: | 1st edition |
| Colección: | Morgan Kaufmann series in systems on silicon.
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627528006719 |
Tabla de Contenidos:
- Cover Page; Network Processors; Copyright Page; Table of Contents; Preface; Chapter 1. Introduction and Motivation; 1.1 Network Processors Ecosystem; 1.2 Communication Systems and Applications; 1.3 Network Elements; 1.4 Network Processors; 1.5 Structure of This Book; 1.6 Summary; Part 1. Networks; Chapter 2. Networking Fundamentals; 2.1 Introduction; 2.2 Networks Primer; 2.3 Data Networking Models; 2.4 Basic Network Technologies; 2.5 Telecom Networks; 2.6 Data Networks; 2.7 Summary; Appendix A: Registration Protocols; Appendix B: Spanning Tree Protocols; Chapter 3. Converged Networks
- 3.1 Introduction3.2 From Telecom Networks to Data Networks; 3.3 From Datacom to Telecom; 3.4 Summary; Appendix A: Routing Information Distribution Protocols; Chapter 4. Access and Home Networks; 4.1 Access Networks; 4.2 Home and Building Networks; 4.3 Summary; Part 2. Processing; Chapter 5. Packet Processing; 5.1 Introduction and Definitions; 5.2 Ingress and Egress; 5.3 Framing; 5.4 Parsing and Classification; 5.5 Search, Lookup, and Forwarding; 5.6 Modification; 5.7 Compression and Encryption; 5.8 Queueing and Traffic Management; 5.9 Summary; Chapter 6. Packet Flow Handling; 6.1 Definitions
- 6.2 Quality of Service6.3 Class of Service; 6.4 QoS Mechanisms; 6.5 Summary; Chapter 7. Architecture; 7.1 Introduction; 7.2 Background and Definitions; 7.3 Equipment Design Alternatives: ASICS Versus NP; 7.4 Network Processors Basic Architectures; 7.5 Instruction Set (Scalability; Processing Speed); 7.6 NP Components; 7.7 Summary; Chapter 8. Software; 8.1 Introduction; 8.2 Conventional Systems; 8.3 Programming Models Classification; 8.4 Parallel Programming; 8.5 Pipelining; 8.6 Network Processor Programming; 8.7 Summary; Appendix A: Parsing and Classification Languages
- Appendix B: Click and NP-Click Language and Programming ModelAppendix C: PPL Language and Programming Model; Chapter 9. NP Peripherals; 9.1 Switch Fabrics; 9.2 Coprocessors; 9.3 Summary; Part 3. A Network Processor: EZchip; Chapter 10. EZchip Architecture, Capabilities, and Applications; 10.1 General Description; 10.2 System Architecture; 10.3 Lookup Structures; 10.4 Counters, Statistics and Rate Control; 10.5 Traffic Management; 10.6 Stateful Classification; 10.7 Multicast Frames; 10.8 Data Flow; 10.9 Summary; Chapter 11. EZchip Programming; 11.1 Instruction Pipeline
- 11.2 Writing NP Microcode11.3 Preprocessor Overview; 11.4 Developing and Running NP Applications; 11.5 Top Common Commands; 11.6 Summary; Appendix A: Preprocessor Commands; Chapter 12. Parsing; 12.1 Internal Engine Diagram; 12.2 Topparse Registers; 12.3 Topparse Structures; 12.4 Topparse Instruction Set; 12.5 Example; 12.6 Summary; Appendix A: Detailed Register Description; Appendix B: Topparse Addressing Modes; Appendix C: Topparse Detailed Instruction Set; Chapter 13. Searching; 13.1 Introduction; 13.2 Internal Engine Diagram; 13.3 Topsearch I Structures
- 13.4 Interface to Topparse (Input to Topsearch)
