Multiprocessor systems-on-chips
Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application ar...
| Otros Autores: | , |
|---|---|
| Formato: | Libro electrónico |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; London :
Morgan Kaufmann
c2005.
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| Edición: | 1st edition |
| Colección: | Morgan Kaufmann series in systems on silicon.
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| Materias: | |
| Ver en Biblioteca Universitat Ramon Llull: | https://discovery.url.edu/permalink/34CSUC_URL/1im36ta/alma991009627277006719 |
Tabla de Contenidos:
- Front Cover; Multiprocessor Systems-on-Chips; Copyright Page; Contents; About the Editors; Preface; Chapter 1. The What, Why, and How of MPSoCs; 1.1 Introduction; 1.2 What are MPSoCs; 1.3 Why MPSoCs?; 1.4 Challenges; 1.5 Design Methodologies; 1.6 Hardware Architectures; 1.7 Software; 1.8 The Rest of the Book; PART I: Hardware; Chapter 2. Techniques for Designing Energy-Aware MPSoCs; 2.1 Introduction; 2.2 Energy-Aware Processor Design; 2.3 Energy-Aware Memory System Design; 2.4 Energy-Aware On-Chip Communication System Design; 2.5 Energy-Aware Software; 2.6 Conclusions
- Chapter 3. Networks on Chips. A New Paradigm for Component-Based MPSoC Design3.1 Introduction; 3.2 Signal Transmission on Chip; 3.3 Micronetwork Architecture and Control; 3.4 Software Layers; 3.5 Conclusions; Chapter 4. Architecture of Embedded Microprocessors; 4.1 Introduction; 4.2 Embedded Versus High-Performance Processors: A Common Foundation; 4.3 Pipelining Techniques; 4.4 Survey of General-purpose 32-bit Embedded Microprocessors; 4.5 Virtual Simple Architecture (VISA). Integrating Non-Determinism Without Undermining Safety; 4.6 Conclusions
- Chapter 5. Performance and Flexibility for Multiple-Processor SoC Design5.1 Introduction; 5.2 The Limitations of Traditional ASIC Design; 5.3 Extensible Processors as an Alternative to RTL; 5.4 Toward Multiple-Processor SoCs; 5.5 Processors and Disruptive Technology; 5.6 Conclusions; Chapter 6. MPSoC Performance Modeling and Analysis; 6.1 Introduction; 6.2 Architecture Component Performance Modeling and Analysis; 6.3 Process Execution Modeling; 6.4 Modeling Shared Resources; 6.5 Global Performance Analysis; 6.6 Conclusions
- Chapter 7. Design of Communication Architectures for High- Performance and Energy-Efficient Systems-on-Chips7.1 Introduction; 7.2 On-Chip Communication Architectures; 7.3 System-Level Analysis for Designing Communication Architectures; 7.4 Design Space Exploration for Customizing Communication Architectures; 7.5 Adaptive Communication Architectures; 7.6 Communication Architectures for Energy/Battery-Efficient Systems; 7.7 Conclusions; Chapter 8. Design Space Exploration of On-Chip Networks: A Case Study; 8.1 Introduction; 8.2 Background; 8.3 Modeling of Data.ow Networks
- 8.4 Case Study: Hiperlan/2 Application8.5 The Architectural Platform; 8.6 Results; 8.7 Conclusions; PART II: SOFTWARE; Chapter 9. Memory Systems and Compiler Support for MPSoC Architectures; 9.1 Introduction and Motivation; 9.2 Memory Architectures; 9.3 Compiler Support; 9.4 Conclusions; Chapter 10. A SystemC-Based Abstract Real-Time Operating System Model for Multiprocessor System-on-Chips; 10.1 Introduction; 10.2 Basic Concepts and Terminology; 10.3 Basic System Model; 10.4 Uniprocessor Systems; 10.5 Multiprocessor Systems; 10.6 Summary
- Chapter 11. Cost-Efficient Mapping of Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems
